[U-Boot] [PATCH V2] arm: armv7: omap3: Fix restore sequence in lowlevel_init

[Jeroen Hofstee]

On 10/07/2012 09:24 PM, Albert ARIBAUD wrote:
> The restore sequence in lowlevel_init was in the wrong order,
> causing lr to lose its original value and be set equal to ip
> instead. Also, its use of the stack clashes with that of
> s_init, so move the s_init call after the restore and turn
> it  into a tail-optimized branch.
>
> Signed-off-by: Albert ARIBAUD <albert.u.boot at aribaud.net>
> ---
> V2: move s_init call after restore and tail-optimize it into a branch
> V1: fix order of restores
>
>   arch/arm/cpu/armv7/omap3/lowlevel_init.S |    9 ++++-----
>   1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
> index ebf69fa..eacfef8 100644
> --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
> +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
> @@ -214,7 +214,7 @@ pll_div_val5:
>   
>   ENTRY(lowlevel_init)
>   	ldr	sp, SRAM_STACK
> -	str	ip, [sp]	/* stash old link register */
> +	str	ip, [sp]	/* stash ip register */
>   	mov	ip, lr		/* save link reg across call */
>   #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
>   /*
> @@ -224,12 +224,11 @@ ENTRY(lowlevel_init)
>   	ldr	r1, =SRAM_CLK_CODE
>   	bl	cpy_clk_code
>   #endif /* NAND Boot */
> -	bl	s_init		/* go setup pll, mux, memory */
> -	ldr	ip, [sp]	/* restore save ip */
>   	mov	lr, ip		/* restore link reg */
> +	ldr	ip, [sp]	/* restore save ip */
> +	/* tail-call s_init to setup pll, mux, memory */
> +	b	s_init
>   
> -	/* back to arch calling code */
> -	mov	pc, lr
>   ENDPROC(lowlevel_init)
>   
>   	/* the literal pools origin */
Tested-by: Jeroen Hofstee <jeroen at myspectrum.nl>

on a tam3517 SOM (am3517 mcu) derived board.

Regards,
Jeroen