[U-Boot] mpc85xx debug TLB entry

[Scott Wood]

I'm debugging some SPL changes and am still having a hard time  
following the initial TLB flow.  We seem to be creating an entry in AS0  
-- how is that not conflicting with the TLB entry we're running from?   
Why is the debug TLB 256K?  Why is it not aligned to 256K?  How do you  
know that MAS2_I is correct (it should be cacheable in the  
loaded-by-spl case)?

I'm trying to get the p2020rdb-pca SPL payload to run out of L2 SRAM,  
and I see weird TLB behavior causing a hang if I don't comment out the  
debug TLB.

-Scott