[U-Boot] [PATCH 5/5] am33xx: support board specific ddr settings

[Tom Rini]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 10/16/12 10:43, Peter Korsgaard wrote:
>>>>>> "Tom" == Tom Rini <trini at ti.com> writes:
> 
> Hi,
> 
> Tom> I would like to see the ddr information kept in Tom>
> arch/arm/cpu/armv7/am33xx but prefixed with vendor/part information
> so Tom> we can re-use it on other boards.
> 
> So something like:
> 
> /* Micron MT41J128M16JT-125 */ #define
> MICRON_MT41J128M16JT125_EMIF_READ_LATENCY	0x06 #define
> MICRON_MT41J128M16JT125_EMIF_TIM1		0x0888A39B ..
> 
> That's seems pretty long, but OK - I can do that.
> 
> The board I'm using has a MT41J64, so those numbers are basically
> the same as the 128 except for the number of rows.

MICRON_MT41J{128,64}M_... then?

- -- 
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://www.enigmail.net/

iQIcBAEBAgAGBQJQfc3fAAoJENk4IS6UOR1WGtwP/2wCuMDhncZM/oSzbcW0Cjsd
eGx1lBit+X7lmaqhIgixFL3Q083DJ6acJ5WAoR5E8m0CFzHBVyoPnHpr9Gz1RQHP
gu9T6VxdPFa4EABE9YyLSaCYmDgETaRUfLiQq3fBztLYwMG3QxkXDgLf05rl9giQ
9s1cXT5S+3DnT8cRg5FHO7fRuq7BJHgHNTW1CrR6wDKNKlx6QrlyyS8aSieaUkdI
3+HWE2vkKETaBXPNUSpJ/iutlgh3PTXmgydAjWSK+biFNb+9kNjzbYwdZBnAgWo0
8tpuaNIqY27zjk3W8erTjF3MB6sCmFUetQoLQcVgXdQYRa242DT3gQhJ0Frlkibt
8vsMVHWewwmJ0OKwcVdcLTB/pG/8u4GKD4EaV4lsxN02SruVrHALraT0mVw3sMV2
lUQd15HE9SAXCX7u/rTa1iCyT1Ll1O8ELrux559wx1R31ob2gLQvwNN9QWeA3Pwf
Gp/9QykTXNB9nSGN5Ri9pJp9YJXxv7aOreD7wMZwQHJ1nefplX+EirkCysaiw3bi
Q8LOoKPLyvKe0eltn4IpYzNTtzRybl79lap8rw7k8IowFlKuE2xzO4SJBIY9SEFB
QNo+lyxrw3Yl95EU41IOB8fq2QElmxJveCQTT07MotkjS1X3nv8ScQfS+dC/SWBL
EkZB1u7ORVcNX3BfGB3q
=NDut
-----END PGP SIGNATURE-----