[U-Boot] [PATCH 07/15] x86: Add functions to access MSRs
Stefan Reinauer
reinauer at google.com
Wed Oct 24 23:15:37 CEST 2012
Graeme,
Reusing code from the Linux kernel is generally a great idea. However for
simplicity I'd rather have 25 lines than 870 lines for reading MSRs. It
seems a lot of code in those files doesn't really apply for u-boot
Stefan
On Tue, Oct 23, 2012 at 9:34 PM, Graeme Russ <graeme.russ at gmail.com> wrote:
> Hi Simon,
>
> On Wed, Oct 24, 2012 at 3:04 PM, Simon Glass <sjg at chromium.org> wrote:
> > From: Stefan Reinauer <reinauer at chromium.org>
> >
> > Provide basic functions to access these registers.
>
> I really should have got my funk into gear and posted patches I
> created (on a side project) a long time ago :(
>
> Anyways - I implemented the same, but I just stole the code from the
> Linux kernel (3.1 to be exact) - I've attached my patch below (may not
> apply cleanly now)
>
> Regards,
>
> Graeme
>
> >
> > Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
> > Signed-off-by: Simon Glass <sjg at chromium.org>
> > ---
> > arch/x86/include/asm/msr.h | 25 +++++++++++++++++++++++++
> > 1 files changed, 25 insertions(+), 0 deletions(-)
> > create mode 100644 arch/x86/include/asm/msr.h
> >
> > diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
> > new file mode 100644
> > index 0000000..0a681d1
> > --- /dev/null
> > +++ b/arch/x86/include/asm/msr.h
> > @@ -0,0 +1,25 @@
> > +#ifndef CPU_X86_ASM_MSR_H
> > +#define CPU_X86_ASM_MSR_H
> > +
> > +static inline uint64_t rdmsr(unsigned index)
> > +{
> > + uint64_t result;
> > +
> > + asm volatile (
> > + "rdmsr"
> > + : "=A" (result)
> > + : "c" (index)
> > + );
> > + return result;
> > +}
> > +
> > +static inline void wrmsr(unsigned index, uint64_t msr)
> > +{
> > + asm volatile (
> > + "wrmsr"
> > + : /* No outputs */
> > + : "c" (index), "A" (msr)
> > + );
> > +}
> > +
> > +#endif /* CPU_X86_ASM_MSR_H */
> > --
> > 1.7.7.3
> >
>
> Zee Patch ;)
>
> x86: Import MSR/MTRR code from Linux
>
> Imported from Linux 3.1 with a few modifications to suit U-Boot
> ---
> arch/x86/include/asm/msr-index.h | 447
> ++++++++++++++++++++++++++++++++++++++
> arch/x86/include/asm/msr.h | 216 ++++++++++++++++++
> arch/x86/include/asm/mtrr.h | 203 +++++++++++++++++
> 3 files changed, 866 insertions(+), 0 deletions(-)
> create mode 100644 arch/x86/include/asm/msr-index.h
> create mode 100644 arch/x86/include/asm/msr.h
> create mode 100644 arch/x86/include/asm/mtrr.h
>
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> new file mode 100644
> index 0000000..2d4a20a
> --- /dev/null
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -0,0 +1,447 @@
> +#ifndef _ASM_X86_MSR_INDEX_H
> +#define _ASM_X86_MSR_INDEX_H
> +
> +/* CPU model specific register (MSR) numbers */
> +
> +/* x86-64 specific MSRs */
> +#define MSR_EFER 0xc0000080 /* extended feature register */
> +#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
> +#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
> +#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
> +#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
> +#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
> +#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
> +#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
> +#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
> +
> +/* EFER bits: */
> +#define _EFER_SCE 0 /* SYSCALL/SYSRET */
> +#define _EFER_LME 8 /* Long mode enable */
> +#define _EFER_LMA 10 /* Long mode active (read-only) */
> +#define _EFER_NX 11 /* No execute enable */
> +#define _EFER_SVME 12 /* Enable virtualization */
> +#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
> +#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
> +
> +#define EFER_SCE (1<<_EFER_SCE)
> +#define EFER_LME (1<<_EFER_LME)
> +#define EFER_LMA (1<<_EFER_LMA)
> +#define EFER_NX (1<<_EFER_NX)
> +#define EFER_SVME (1<<_EFER_SVME)
> +#define EFER_LMSLE (1<<_EFER_LMSLE)
> +#define EFER_FFXSR (1<<_EFER_FFXSR)
> +
> +/* Intel MSRs. Some also available on other CPUs */
> +#define MSR_IA32_PERFCTR0 0x000000c1
> +#define MSR_IA32_PERFCTR1 0x000000c2
> +#define MSR_FSB_FREQ 0x000000cd
> +
> +#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
> +#define NHM_C3_AUTO_DEMOTE (1UL << 25)
> +#define NHM_C1_AUTO_DEMOTE (1UL << 26)
> +#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
> +
> +#define MSR_MTRRcap 0x000000fe
> +#define MSR_IA32_BBL_CR_CTL 0x00000119
> +#define MSR_IA32_BBL_CR_CTL3 0x0000011e
> +
> +#define MSR_IA32_SYSENTER_CS 0x00000174
> +#define MSR_IA32_SYSENTER_ESP 0x00000175
> +#define MSR_IA32_SYSENTER_EIP 0x00000176
> +
> +#define MSR_IA32_MCG_CAP 0x00000179
> +#define MSR_IA32_MCG_STATUS 0x0000017a
> +#define MSR_IA32_MCG_CTL 0x0000017b
> +
> +#define MSR_OFFCORE_RSP_0 0x000001a6
> +#define MSR_OFFCORE_RSP_1 0x000001a7
> +
> +#define MSR_IA32_PEBS_ENABLE 0x000003f1
> +#define MSR_IA32_DS_AREA 0x00000600
> +#define MSR_IA32_PERF_CAPABILITIES 0x00000345
> +
> +#define MSR_MTRRfix64K_00000 0x00000250
> +#define MSR_MTRRfix16K_80000 0x00000258
> +#define MSR_MTRRfix16K_A0000 0x00000259
> +#define MSR_MTRRfix4K_C0000 0x00000268
> +#define MSR_MTRRfix4K_C8000 0x00000269
> +#define MSR_MTRRfix4K_D0000 0x0000026a
> +#define MSR_MTRRfix4K_D8000 0x0000026b
> +#define MSR_MTRRfix4K_E0000 0x0000026c
> +#define MSR_MTRRfix4K_E8000 0x0000026d
> +#define MSR_MTRRfix4K_F0000 0x0000026e
> +#define MSR_MTRRfix4K_F8000 0x0000026f
> +#define MSR_MTRRdefType 0x000002ff
> +
> +#define MSR_IA32_CR_PAT 0x00000277
> +
> +#define MSR_IA32_DEBUGCTLMSR 0x000001d9
> +#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
> +#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
> +#define MSR_IA32_LASTINTFROMIP 0x000001dd
> +#define MSR_IA32_LASTINTTOIP 0x000001de
> +
> +/* DEBUGCTLMSR bits (others vary by model): */
> +#define DEBUGCTLMSR_LBR (1UL << 0)
> +#define DEBUGCTLMSR_BTF (1UL << 1)
> +#define DEBUGCTLMSR_TR (1UL << 6)
> +#define DEBUGCTLMSR_BTS (1UL << 7)
> +#define DEBUGCTLMSR_BTINT (1UL << 8)
> +#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
> +#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
> +#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
> +
> +#define MSR_IA32_MC0_CTL 0x00000400
> +#define MSR_IA32_MC0_STATUS 0x00000401
> +#define MSR_IA32_MC0_ADDR 0x00000402
> +#define MSR_IA32_MC0_MISC 0x00000403
> +
> +#define MSR_AMD64_MC0_MASK 0xc0010044
> +
> +#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
> +#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
> +#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
> +#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
> +
> +#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
> +
> +/* These are consecutive and not in the normal 4er MCE bank block */
> +#define MSR_IA32_MC0_CTL2 0x00000280
> +#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
> +
> +#define MSR_P6_PERFCTR0 0x000000c1
> +#define MSR_P6_PERFCTR1 0x000000c2
> +#define MSR_P6_EVNTSEL0 0x00000186
> +#define MSR_P6_EVNTSEL1 0x00000187
> +
> +/* AMD64 MSRs. Not complete. See the architecture manual for a more
> + complete list. */
> +
> +#define MSR_AMD64_PATCH_LEVEL 0x0000008b
> +#define MSR_AMD64_NB_CFG 0xc001001f
> +#define MSR_AMD64_PATCH_LOADER 0xc0010020
> +#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
> +#define MSR_AMD64_OSVW_STATUS 0xc0010141
> +#define MSR_AMD64_DC_CFG 0xc0011022
> +#define MSR_AMD64_IBSFETCHCTL 0xc0011030
> +#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
> +#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
> +#define MSR_AMD64_IBSOPCTL 0xc0011033
> +#define MSR_AMD64_IBSOPRIP 0xc0011034
> +#define MSR_AMD64_IBSOPDATA 0xc0011035
> +#define MSR_AMD64_IBSOPDATA2 0xc0011036
> +#define MSR_AMD64_IBSOPDATA3 0xc0011037
> +#define MSR_AMD64_IBSDCLINAD 0xc0011038
> +#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
> +#define MSR_AMD64_IBSCTL 0xc001103a
> +#define MSR_AMD64_IBSBRTARGET 0xc001103b
> +
> +/* Fam 15h MSRs */
> +#define MSR_F15H_PERF_CTL 0xc0010200
> +#define MSR_F15H_PERF_CTR 0xc0010201
> +
> +/* Fam 10h MSRs */
> +#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
> +#define FAM10H_MMIO_CONF_ENABLE (1<<0)
> +#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
> +#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
> +#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
> +#define FAM10H_MMIO_CONF_BASE_SHIFT 20
> +#define MSR_FAM10H_NODE_ID 0xc001100c
> +
> +/* K8 MSRs */
> +#define MSR_K8_TOP_MEM1 0xc001001a
> +#define MSR_K8_TOP_MEM2 0xc001001d
> +#define MSR_K8_SYSCFG 0xc0010010
> +#define MSR_K8_INT_PENDING_MSG 0xc0010055
> +/* C1E active bits in int pending message */
> +#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
> +#define MSR_K8_TSEG_ADDR 0xc0010112
> +#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit
> */
> +#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit
> */
> +#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem
> */
> +
> +/* K7 MSRs */
> +#define MSR_K7_EVNTSEL0 0xc0010000
> +#define MSR_K7_PERFCTR0 0xc0010004
> +#define MSR_K7_EVNTSEL1 0xc0010001
> +#define MSR_K7_PERFCTR1 0xc0010005
> +#define MSR_K7_EVNTSEL2 0xc0010002
> +#define MSR_K7_PERFCTR2 0xc0010006
> +#define MSR_K7_EVNTSEL3 0xc0010003
> +#define MSR_K7_PERFCTR3 0xc0010007
> +#define MSR_K7_CLK_CTL 0xc001001b
> +#define MSR_K7_HWCR 0xc0010015
> +#define MSR_K7_FID_VID_CTL 0xc0010041
> +#define MSR_K7_FID_VID_STATUS 0xc0010042
> +
> +/* K6 MSRs */
> +#define MSR_K6_WHCR 0xc0000082
> +#define MSR_K6_UWCCR 0xc0000085
> +#define MSR_K6_EPMR 0xc0000086
> +#define MSR_K6_PSOR 0xc0000087
> +#define MSR_K6_PFIR 0xc0000088
> +
> +/* Centaur-Hauls/IDT defined MSRs. */
> +#define MSR_IDT_FCR1 0x00000107
> +#define MSR_IDT_FCR2 0x00000108
> +#define MSR_IDT_FCR3 0x00000109
> +#define MSR_IDT_FCR4 0x0000010a
> +
> +#define MSR_IDT_MCR0 0x00000110
> +#define MSR_IDT_MCR1 0x00000111
> +#define MSR_IDT_MCR2 0x00000112
> +#define MSR_IDT_MCR3 0x00000113
> +#define MSR_IDT_MCR4 0x00000114
> +#define MSR_IDT_MCR5 0x00000115
> +#define MSR_IDT_MCR6 0x00000116
> +#define MSR_IDT_MCR7 0x00000117
> +#define MSR_IDT_MCR_CTRL 0x00000120
> +
> +/* VIA Cyrix defined MSRs*/
> +#define MSR_VIA_FCR 0x00001107
> +#define MSR_VIA_LONGHAUL 0x0000110a
> +#define MSR_VIA_RNG 0x0000110b
> +#define MSR_VIA_BCR2 0x00001147
> +
> +/* Transmeta defined MSRs */
> +#define MSR_TMTA_LONGRUN_CTRL 0x80868010
> +#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
> +#define MSR_TMTA_LRTI_READOUT 0x80868018
> +#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
> +
> +/* Intel defined MSRs. */
> +#define MSR_IA32_P5_MC_ADDR 0x00000000
> +#define MSR_IA32_P5_MC_TYPE 0x00000001
> +#define MSR_IA32_TSC 0x00000010
> +#define MSR_IA32_PLATFORM_ID 0x00000017
> +#define MSR_IA32_EBL_CR_POWERON 0x0000002a
> +#define MSR_EBC_FREQUENCY_ID 0x0000002c
> +#define MSR_IA32_FEATURE_CONTROL 0x0000003a
> +
> +#define FEATURE_CONTROL_LOCKED (1<<0)
> +#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
> +#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
> +
> +#define MSR_IA32_APICBASE 0x0000001b
> +#define MSR_IA32_APICBASE_BSP (1<<8)
> +#define MSR_IA32_APICBASE_ENABLE (1<<11)
> +#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
> +
> +#define MSR_IA32_UCODE_WRITE 0x00000079
> +#define MSR_IA32_UCODE_REV 0x0000008b
> +
> +#define MSR_IA32_PERF_STATUS 0x00000198
> +#define MSR_IA32_PERF_CTL 0x00000199
> +
> +#define MSR_IA32_MPERF 0x000000e7
> +#define MSR_IA32_APERF 0x000000e8
> +
> +#define MSR_IA32_THERM_CONTROL 0x0000019a
> +#define MSR_IA32_THERM_INTERRUPT 0x0000019b
> +
> +#define THERM_INT_HIGH_ENABLE (1 << 0)
> +#define THERM_INT_LOW_ENABLE (1 << 1)
> +#define THERM_INT_PLN_ENABLE (1 << 24)
> +
> +#define MSR_IA32_THERM_STATUS 0x0000019c
> +
> +#define THERM_STATUS_PROCHOT (1 << 0)
> +#define THERM_STATUS_POWER_LIMIT (1 << 10)
> +
> +#define MSR_THERM2_CTL 0x0000019d
> +
> +#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
> +
> +#define MSR_IA32_MISC_ENABLE 0x000001a0
> +
> +#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
> +
> +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
> +
> +#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
> +
> +#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
> +#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
> +
> +#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
> +
> +#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
> +#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
> +#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
> +
> +/* Thermal Thresholds Support */
> +#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
> +#define THERM_SHIFT_THRESHOLD0 8
> +#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
> +#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
> +#define THERM_SHIFT_THRESHOLD1 16
> +#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
> +#define THERM_STATUS_THRESHOLD0 (1 << 6)
> +#define THERM_LOG_THRESHOLD0 (1 << 7)
> +#define THERM_STATUS_THRESHOLD1 (1 << 8)
> +#define THERM_LOG_THRESHOLD1 (1 << 9)
> +
> +/* MISC_ENABLE bits: architectural */
> +#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
> +#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
> +#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
> +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
> +#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
> +#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
> +#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
> +#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
> +#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
> +#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
> +
> +/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
> +#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
> +#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
> +#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
> +#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
> +#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
> +#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
> +#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
> +#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
> +#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
> +#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
> +#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
> +#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
> +#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
> +#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
> +#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
> +
> +/* P4/Xeon+ specific */
> +#define MSR_IA32_MCG_EAX 0x00000180
> +#define MSR_IA32_MCG_EBX 0x00000181
> +#define MSR_IA32_MCG_ECX 0x00000182
> +#define MSR_IA32_MCG_EDX 0x00000183
> +#define MSR_IA32_MCG_ESI 0x00000184
> +#define MSR_IA32_MCG_EDI 0x00000185
> +#define MSR_IA32_MCG_EBP 0x00000186
> +#define MSR_IA32_MCG_ESP 0x00000187
> +#define MSR_IA32_MCG_EFLAGS 0x00000188
> +#define MSR_IA32_MCG_EIP 0x00000189
> +#define MSR_IA32_MCG_RESERVED 0x0000018a
> +
> +/* Pentium IV performance counter MSRs */
> +#define MSR_P4_BPU_PERFCTR0 0x00000300
> +#define MSR_P4_BPU_PERFCTR1 0x00000301
> +#define MSR_P4_BPU_PERFCTR2 0x00000302
> +#define MSR_P4_BPU_PERFCTR3 0x00000303
> +#define MSR_P4_MS_PERFCTR0 0x00000304
> +#define MSR_P4_MS_PERFCTR1 0x00000305
> +#define MSR_P4_MS_PERFCTR2 0x00000306
> +#define MSR_P4_MS_PERFCTR3 0x00000307
> +#define MSR_P4_FLAME_PERFCTR0 0x00000308
> +#define MSR_P4_FLAME_PERFCTR1 0x00000309
> +#define MSR_P4_FLAME_PERFCTR2 0x0000030a
> +#define MSR_P4_FLAME_PERFCTR3 0x0000030b
> +#define MSR_P4_IQ_PERFCTR0 0x0000030c
> +#define MSR_P4_IQ_PERFCTR1 0x0000030d
> +#define MSR_P4_IQ_PERFCTR2 0x0000030e
> +#define MSR_P4_IQ_PERFCTR3 0x0000030f
> +#define MSR_P4_IQ_PERFCTR4 0x00000310
> +#define MSR_P4_IQ_PERFCTR5 0x00000311
> +#define MSR_P4_BPU_CCCR0 0x00000360
> +#define MSR_P4_BPU_CCCR1 0x00000361
> +#define MSR_P4_BPU_CCCR2 0x00000362
> +#define MSR_P4_BPU_CCCR3 0x00000363
> +#define MSR_P4_MS_CCCR0 0x00000364
> +#define MSR_P4_MS_CCCR1 0x00000365
> +#define MSR_P4_MS_CCCR2 0x00000366
> +#define MSR_P4_MS_CCCR3 0x00000367
> +#define MSR_P4_FLAME_CCCR0 0x00000368
> +#define MSR_P4_FLAME_CCCR1 0x00000369
> +#define MSR_P4_FLAME_CCCR2 0x0000036a
> +#define MSR_P4_FLAME_CCCR3 0x0000036b
> +#define MSR_P4_IQ_CCCR0 0x0000036c
> +#define MSR_P4_IQ_CCCR1 0x0000036d
> +#define MSR_P4_IQ_CCCR2 0x0000036e
> +#define MSR_P4_IQ_CCCR3 0x0000036f
> +#define MSR_P4_IQ_CCCR4 0x00000370
> +#define MSR_P4_IQ_CCCR5 0x00000371
> +#define MSR_P4_ALF_ESCR0 0x000003ca
> +#define MSR_P4_ALF_ESCR1 0x000003cb
> +#define MSR_P4_BPU_ESCR0 0x000003b2
> +#define MSR_P4_BPU_ESCR1 0x000003b3
> +#define MSR_P4_BSU_ESCR0 0x000003a0
> +#define MSR_P4_BSU_ESCR1 0x000003a1
> +#define MSR_P4_CRU_ESCR0 0x000003b8
> +#define MSR_P4_CRU_ESCR1 0x000003b9
> +#define MSR_P4_CRU_ESCR2 0x000003cc
> +#define MSR_P4_CRU_ESCR3 0x000003cd
> +#define MSR_P4_CRU_ESCR4 0x000003e0
> +#define MSR_P4_CRU_ESCR5 0x000003e1
> +#define MSR_P4_DAC_ESCR0 0x000003a8
> +#define MSR_P4_DAC_ESCR1 0x000003a9
> +#define MSR_P4_FIRM_ESCR0 0x000003a4
> +#define MSR_P4_FIRM_ESCR1 0x000003a5
> +#define MSR_P4_FLAME_ESCR0 0x000003a6
> +#define MSR_P4_FLAME_ESCR1 0x000003a7
> +#define MSR_P4_FSB_ESCR0 0x000003a2
> +#define MSR_P4_FSB_ESCR1 0x000003a3
> +#define MSR_P4_IQ_ESCR0 0x000003ba
> +#define MSR_P4_IQ_ESCR1 0x000003bb
> +#define MSR_P4_IS_ESCR0 0x000003b4
> +#define MSR_P4_IS_ESCR1 0x000003b5
> +#define MSR_P4_ITLB_ESCR0 0x000003b6
> +#define MSR_P4_ITLB_ESCR1 0x000003b7
> +#define MSR_P4_IX_ESCR0 0x000003c8
> +#define MSR_P4_IX_ESCR1 0x000003c9
> +#define MSR_P4_MOB_ESCR0 0x000003aa
> +#define MSR_P4_MOB_ESCR1 0x000003ab
> +#define MSR_P4_MS_ESCR0 0x000003c0
> +#define MSR_P4_MS_ESCR1 0x000003c1
> +#define MSR_P4_PMH_ESCR0 0x000003ac
> +#define MSR_P4_PMH_ESCR1 0x000003ad
> +#define MSR_P4_RAT_ESCR0 0x000003bc
> +#define MSR_P4_RAT_ESCR1 0x000003bd
> +#define MSR_P4_SAAT_ESCR0 0x000003ae
> +#define MSR_P4_SAAT_ESCR1 0x000003af
> +#define MSR_P4_SSU_ESCR0 0x000003be
> +#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual
> */
> +
> +#define MSR_P4_TBPU_ESCR0 0x000003c2
> +#define MSR_P4_TBPU_ESCR1 0x000003c3
> +#define MSR_P4_TC_ESCR0 0x000003c4
> +#define MSR_P4_TC_ESCR1 0x000003c5
> +#define MSR_P4_U2L_ESCR0 0x000003b0
> +#define MSR_P4_U2L_ESCR1 0x000003b1
> +
> +#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
> +
> +/* Intel Core-based CPU performance counters */
> +#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
> +#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
> +#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
> +#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
> +#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
> +#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
> +#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
> +
> +/* Geode defined MSRs */
> +#define MSR_GEODE_BUSCONT_CONF0 0x00001900
> +
> +/* Intel VT MSRs */
> +#define MSR_IA32_VMX_BASIC 0x00000480
> +#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
> +#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
> +#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
> +#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
> +#define MSR_IA32_VMX_MISC 0x00000485
> +#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
> +#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
> +#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
> +#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
> +#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
> +#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
> +#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
> +
> +/* AMD-V MSRs */
> +
> +#define MSR_VM_CR 0xc0010114
> +#define MSR_VM_IGNNE 0xc0010115
> +#define MSR_VM_HSAVE_PA 0xc0010117
> +
> +#endif /* _ASM_X86_MSR_INDEX_H */
> diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
> new file mode 100644
> index 0000000..1865c64
> --- /dev/null
> +++ b/arch/x86/include/asm/msr.h
> @@ -0,0 +1,216 @@
> +#ifndef _ASM_X86_MSR_H
> +#define _ASM_X86_MSR_H
> +
> +#include <asm/msr-index.h>
> +
> +#ifndef __ASSEMBLY__
> +
> +#include <linux/types.h>
> +#include <linux/ioctl.h>
> +
> +#define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8])
> +#define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8])
> +
> +#ifdef __KERNEL__
> +
> +#include <asm/errno.h>
> +
> +struct msr {
> + union {
> + struct {
> + u32 l;
> + u32 h;
> + };
> + u64 q;
> + };
> +};
> +
> +struct msr_info {
> + u32 msr_no;
> + struct msr reg;
> + struct msr *msrs;
> + int err;
> +};
> +
> +struct msr_regs_info {
> + u32 *regs;
> + int err;
> +};
> +
> +static inline unsigned long long native_read_tscp(unsigned int *aux)
> +{
> + unsigned long low, high;
> + asm volatile(".byte 0x0f,0x01,0xf9"
> + : "=a" (low), "=d" (high), "=c" (*aux));
> + return low | ((u64)high << 32);
> +}
> +
> +/*
> + * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
> + * constraint has different meanings. For i386, "A" means exactly
> + * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
> + * it means rax *or* rdx.
> + */
> +#ifdef CONFIG_X86_64
> +#define DECLARE_ARGS(val, low, high) unsigned low, high
> +#define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32))
> +#define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high)
> +#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
> +#else
> +#define DECLARE_ARGS(val, low, high) unsigned long long val
> +#define EAX_EDX_VAL(val, low, high) (val)
> +#define EAX_EDX_ARGS(val, low, high) "A" (val)
> +#define EAX_EDX_RET(val, low, high) "=A" (val)
> +#endif
> +
> +static inline unsigned long long native_read_msr(unsigned int msr)
> +{
> + DECLARE_ARGS(val, low, high);
> +
> + asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
> + return EAX_EDX_VAL(val, low, high);
> +}
> +
> +static inline void native_write_msr(unsigned int msr,
> + unsigned low, unsigned high)
> +{
> + asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) :
> "memory");
> +}
> +
> +extern unsigned long long native_read_tsc(void);
> +
> +extern int native_rdmsr_safe_regs(u32 regs[8]);
> +extern int native_wrmsr_safe_regs(u32 regs[8]);
> +
> +static inline unsigned long long native_read_pmc(int counter)
> +{
> + DECLARE_ARGS(val, low, high);
> +
> + asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c"
> (counter));
> + return EAX_EDX_VAL(val, low, high);
> +}
> +
> +#ifdef CONFIG_PARAVIRT
> +#include <asm/paravirt.h>
> +#else
> +#include <errno.h>
> +/*
> + * Access to machine-specific registers (available on 586 and better only)
> + * Note: the rd* operations modify the parameters directly (without using
> + * pointer indirection), this allows gcc to optimize better
> + */
> +
> +#define rdmsr(msr, val1, val2) \
> +do { \
> + u64 __val = native_read_msr((msr)); \
> + (void)((val1) = (u32)__val); \
> + (void)((val2) = (u32)(__val >> 32)); \
> +} while (0)
> +
> +static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
> +{
> + native_write_msr(msr, low, high);
> +}
> +
> +#define rdmsrl(msr, val) \
> + ((val) = native_read_msr((msr)))
> +
> +#define wrmsrl(msr, val) \
> + native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
> +
> +/* rdmsr with exception handling */
> +#define rdmsr_safe(msr, p1, p2) \
> +({ \
> + int __err; \
> + u64 __val = native_read_msr_safe((msr), &__err); \
> + (*p1) = (u32)__val; \
> + (*p2) = (u32)(__val >> 32); \
> + __err; \
> +})
> +
> +static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
> +{
> + u32 gprs[8] = { 0 };
> + int err;
> +
> + gprs[1] = msr;
> + gprs[7] = 0x9c5a203a;
> +
> + err = native_rdmsr_safe_regs(gprs);
> +
> + *p = gprs[0] | ((u64)gprs[2] << 32);
> +
> + return err;
> +}
> +
> +static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
> +{
> + u32 gprs[8] = { 0 };
> +
> + gprs[0] = (u32)val;
> + gprs[1] = msr;
> + gprs[2] = val >> 32;
> + gprs[7] = 0x9c5a203a;
> +
> + return native_wrmsr_safe_regs(gprs);
> +}
> +
> +static inline int rdmsr_safe_regs(u32 regs[8])
> +{
> + return native_rdmsr_safe_regs(regs);
> +}
> +
> +static inline int wrmsr_safe_regs(u32 regs[8])
> +{
> + return native_wrmsr_safe_regs(regs);
> +}
> +
> +#define rdtscl(low) \
> + ((low) = (u32)__native_read_tsc())
> +
> +#define rdtscll(val) \
> + ((val) = __native_read_tsc())
> +
> +#define rdpmc(counter, low, high) \
> +do { \
> + u64 _l = native_read_pmc((counter)); \
> + (low) = (u32)_l; \
> + (high) = (u32)(_l >> 32); \
> +} while (0)
> +
> +#define rdtscp(low, high, aux) \
> +do { \
> + unsigned long long _val = native_read_tscp(&(aux)); \
> + (low) = (u32)_val; \
> + (high) = (u32)(_val >> 32); \
> +} while (0)
> +
> +#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
> +
> +#endif /* !CONFIG_PARAVIRT */
> +
> +
> +#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),
> \
> + (u32)((val) >> 32))
> +
> +#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
> +
> +#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
> +
> +struct msr *msrs_alloc(void);
> +void msrs_free(struct msr *msrs);
> +
> +#ifdef CONFIG_SMP
> +int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
> +int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
> +void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr
> *msrs);
> +void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr
> *msrs);
> +int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
> +int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
> +int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
> +int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
> +
> +#endif /* CONFIG_SMP */
> +#endif /* __KERNEL__ */
> +#endif /* __ASSEMBLY__ */
> +#endif /* _ASM_X86_MSR_H */
> diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
> new file mode 100644
> index 0000000..b75203c
> --- /dev/null
> +++ b/arch/x86/include/asm/mtrr.h
> @@ -0,0 +1,203 @@
> +/* Generic MTRR (Memory Type Range Register) ioctls.
> +
> + Copyright (C) 1997-1999 Richard Gooch
> +
> + This library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Library General Public
> + License as published by the Free Software Foundation; either
> + version 2 of the License, or (at your option) any later version.
> +
> + This library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Library General Public License for more details.
> +
> + You should have received a copy of the GNU Library General Public
> + License along with this library; if not, write to the Free
> + Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> +
> + Richard Gooch may be reached by email at rgooch at atnf.csiro.au
> + The postal address is:
> + Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121,
> Australia.
> +*/
> +#ifndef _ASM_X86_MTRR_H
> +#define _ASM_X86_MTRR_H
> +
> +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
> +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
> +
> +#ifndef __ASSEMBLY__
> +
> +#include <linux/types.h>
> +#include <linux/ioctl.h>
> +#include <errno.h>
> +
> +#define MTRR_IOCTL_BASE 'M'
> +
> +struct mtrr_sentry {
> + unsigned long base; /* Base address */
> + unsigned int size; /* Size of region */
> + unsigned int type; /* Type of region */
> +};
> +
> +/*
> + * Warning: this structure has a different order from i386
> + * on x86-64. The 32bit emulation code takes care of that.
> + * But you need to use this for 64bit, otherwise your X server
> + * will break.
> + */
> +
> +#ifdef __i386__
> +struct mtrr_gentry {
> + unsigned int regnum; /* Register number */
> + unsigned long base; /* Base address */
> + unsigned int size; /* Size of region */
> + unsigned int type; /* Type of region */
> +};
> +
> +#else /* __i386__ */
> +
> +struct mtrr_gentry {
> + unsigned long base; /* Base address */
> + unsigned int size; /* Size of region */
> + unsigned int regnum; /* Register number */
> + unsigned int type; /* Type of region */
> +};
> +#endif /* !__i386__ */
> +
> +struct mtrr_var_range {
> + __u32 base_lo;
> + __u32 base_hi;
> + __u32 mask_lo;
> + __u32 mask_hi;
> +};
> +
> +/*
> + * In the Intel processor's MTRR interface, the MTRR type is always held
> in
> + * an 8 bit field:
> + */
> +typedef __u8 mtrr_type;
> +
> +#define MTRR_NUM_FIXED_RANGES 88
> +#define MTRR_MAX_VAR_RANGES 256
> +
> +struct mtrr_state_type {
> + struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES];
> + mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES];
> + unsigned char enabled;
> + unsigned char have_fixed;
> + mtrr_type def_type;
> +};
> +
> +/* These are the various ioctls */
> +#define MTRRIOC_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct
> mtrr_sentry)
> +#define MTRRIOC_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct
> mtrr_sentry)
> +#define MTRRIOC_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct
> mtrr_sentry)
> +#define MTRRIOC_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct
> mtrr_gentry)
> +#define MTRRIOC_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct
> mtrr_sentry)
> +#define MTRRIOC_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct
> mtrr_sentry)
> +#define MTRRIOC_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct
> mtrr_sentry)
> +#define MTRRIOC_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct
> mtrr_sentry)
> +#define MTRRIOC_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct
> mtrr_gentry)
> +#define MTRRIOC_KILL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 9, struct
> mtrr_sentry)
> +
> +/* These are the region types */
> +#define MTRR_TYPE_UNCACHABLE 0
> +#define MTRR_TYPE_WRCOMB 1
> +/*#define MTRR_TYPE_ 2*/
> +/*#define MTRR_TYPE_ 3*/
> +#define MTRR_TYPE_WRTHROUGH 4
> +#define MTRR_TYPE_WRPROT 5
> +#define MTRR_TYPE_WRBACK 6
> +#define MTRR_NUM_TYPES 7
> +
> +#ifdef __KERNEL__
> +
> +/* The following functions are for use by other drivers */
> +# ifdef CONFIG_MTRR
> +extern u8 mtrr_type_lookup(u64 addr, u64 end);
> +extern void mtrr_save_fixed_ranges(void *);
> +extern void mtrr_save_state(void);
> +extern int mtrr_add(unsigned long base, unsigned long size,
> + unsigned int type, bool increment);
> +extern int mtrr_add_page(unsigned long base, unsigned long size,
> + unsigned int type, bool increment);
> +extern int mtrr_del(int reg, unsigned long base, unsigned long size);
> +extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
> +extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
> +extern void mtrr_ap_init(void);
> +extern void mtrr_bp_init(void);
> +extern void set_mtrr_aps_delayed_init(void);
> +extern void mtrr_aps_init(void);
> +extern void mtrr_bp_restore(void);
> +extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
> +extern int amd_special_default_mtrr(void);
> +# else
> +static inline u8 mtrr_type_lookup(u64 addr, u64 end)
> +{
> + /*
> + * Return no-MTRRs:
> + */
> + return 0xff;
> +}
> +#define mtrr_save_fixed_ranges(arg) do {} while (0)
> +#define mtrr_save_state() do {} while (0)
> +static inline int mtrr_del(int reg, unsigned long base, unsigned long
> size)
> +{
> + return -ENODEV;
> +}
> +static inline int mtrr_del_page(int reg, unsigned long base, unsigned
> long size)
> +{
> + return -ENODEV;
> +}
> +static inline int mtrr_trim_uncached_memory(unsigned long end_pfn)
> +{
> + return 0;
> +}
> +static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
> +{
> +}
> +
> +#define mtrr_ap_init() do {} while (0)
> +#define mtrr_bp_init() do {} while (0)
> +#define set_mtrr_aps_delayed_init() do {} while (0)
> +#define mtrr_aps_init() do {} while (0)
> +#define mtrr_bp_restore() do {} while (0)
> +# endif
> +
> +#ifdef CONFIG_COMPAT
> +#include <linux/compat.h>
> +
> +struct mtrr_sentry32 {
> + compat_ulong_t base; /* Base address */
> + compat_uint_t size; /* Size of region */
> + compat_uint_t type; /* Type of region */
> +};
> +
> +struct mtrr_gentry32 {
> + compat_ulong_t regnum; /* Register number */
> + compat_uint_t base; /* Base address */
> + compat_uint_t size; /* Size of region */
> + compat_uint_t type; /* Type of region */
> +};
> +
> +#define MTRR_IOCTL_BASE 'M'
> +
> +#define MTRRIOC32_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct
> mtrr_sentry32)
> +#define MTRRIOC32_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct
> mtrr_sentry32)
> +#define MTRRIOC32_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct
> mtrr_sentry32)
> +#define MTRRIOC32_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct
> mtrr_gentry32)
> +#define MTRRIOC32_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct
> mtrr_sentry32)
> +#define MTRRIOC32_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct
> mtrr_sentry32)
> +#define MTRRIOC32_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct
> mtrr_sentry32)
> +#define MTRRIOC32_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct
> mtrr_sentry32)
> +#define MTRRIOC32_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct
> mtrr_gentry32)
> +#define MTRRIOC32_KILL_PAGE_ENTRY \
> + _IOW(MTRR_IOCTL_BASE, 9, struct
> mtrr_sentry32)
> +#endif /* CONFIG_COMPAT */
> +
> +#endif /* __KERNEL__ */
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _ASM_X86_MTRR_H */
> --
> 1.7.7.6
>
--
Stefan Reinauer
Google Inc.
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