[U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state

[Prabhakar Kushwaha]

On 10/30/2012 07:34 AM, Scott Wood wrote:
> Previously, in many if not all configs we were creating overlapping TLB entries
> which is illegal.  This caused a crash during boot when moving p2020rdb NAND SPL
> into L2 SRAM.
>
> Signed-off-by: Scott Wood <scottwood at freescale.com>
> Cc: Prabhakar Kushwaha <prabhakar at freescale.com>
> Cc: Andy Fleming <afleming at freescale.com>
> --
> Prabhakar, please test that debug still works.
>

During RAMBOOT, both "temporary debug TLB entry" and "execution TLB 
entry" is same. So moving "temporary debug TLB  entry" creation after 
"execution TLB entry resizing" will make sure of debugging during NAND 
ramboot, SPI and SD boot.

But for NOR  & NAND SPL there is a problem because boot-up TLB as 
0xfffff000 and temporary debug TLB as 0xEFF80000. So we require to 
create temporary TLB entry to support early debugging.

I will suggest to split the CONFIG_SYS_PPC_E500_DEBUG_TLB define into 2 
parts.
  1)  For NOR , NAND spl debugging
  2)  For RAMBoot:  After resizing of execution TLB

I made following changes in the patch and tested across P1010RDB for 
NOR, NAND-SPL, NAND Ramboot and SPI boot debugging.

Please note I used only this patch after replacing MINIMAL_SPL  with 
CONFIG_NAND_SPL.

diff --git a/arch/powerpc/cpu/mpc85xx/start.S 
b/arch/powerpc/cpu/mpc85xx/start.S
index ac17f9d..c00db4a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -282,7 +282,7 @@ l2_disabled:
         isync
         .endm

-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
  /*
   * TLB entry for debuggging in AS1
   * Create temporary TLB entry in AS0 to handle debug exception
@@ -309,16 +309,6 @@ l2_disabled:
                 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
                 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
                 0, r6
-#else
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
- * because "nexti" will resize TLB to 4K
- */
-       create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
-               0, BOOKE_PAGESZ_256K, \
-               CONFIG_SYS_MONITOR_BASE, MAS2_I, \
-               CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
-               0, r6
  #endif
  #endif

@@ -520,6 +510,24 @@ nexti:     mflr    r1              /* R1 = our PC */
         msync
         tlbwe

+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)\
+   && defined(CONFIG_SYS_RAMBOOT)
+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception 
generated
+ * in AS1.
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * because "nexti" has resized  execution TLB entry to 4K
+ */
+       create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+               0, BOOKE_PAGESZ_256K, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000, 
MAS3_SX|MAS3_SW|MAS3_SR, \
+               0, r6
+#endif
+
  /*
   * Clear out any other TLB entries that may exist, to avoid conflicts.
   * Our TLB entry is in r14.
@@ -534,7 +542,7 @@ nexti:      mflr    r1              /* R1 = our PC */
         li      r3, 0
         mtspr   MAS1, r3
  1:     cmpw    r3, r14
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
         cmpwi   cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
         cror    cr0*4+eq, cr0*4+eq, cr1*4+eq
  #endif

Regards,
Prabhakar