[U-Boot] [PATCH 5/7] mx35: Fix clock dividers

[Stefano Babic]

On 03/09/2012 17:31, Benoît Thébaudeau wrote:
> Hi Stefano,
> 

Hi Benoît,

>> It seems also to me that the current code is wrong if
>> MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in
>> figure
>> 5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the
>> second multiplier comes.
> 
> It looks like the current code is based on a pre(PRDF)-/post(PODF)-divider
> scheme. 

I thought the same.

> Perhaps the first silicon revision was different and incompatible, or it
> was just a bug in the older revisions of the reference manual. The history of
> the reference manual says that this figure and some CCM register descriptions
> have been updated at some point. Anyway, Linux does like my patch.
> 
>>> +		div = CCM_GET_DIVIDER(pdr4,
>>>  			MXC_CCM_PDR4_PER0_PODF_MASK,
>>> -			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
>>> +			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
>>
>> The name remains quite confusing. In the manual is PER0_DIV, which is
>> the meaning of PODF here ?
> 
> It the abbreviation FSL uses for post-dividers. If the pre-divider is merged
> with the post-divider to form a single divider, the naming from the RM makes
> more sense. Do you want a new version changing this naming?

Yes, make this small change - then from my point of view I am ready to
merge it.

Regards,
Stefano



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