[U-Boot] [PATCH] powerpc mpc85xx: Synchronization Required for mmucsr0 spr
Scott Wood
scottwood at freescale.com
Fri Sep 7 20:50:21 CEST 2012
On 09/07/2012 07:25 AM, Laurent Joye wrote:
> As explained in the PowerPC e500 Core Family Reference Manual
> (Synchronization Requirements for SPRs), an isync instruction
> is required after a mtspr mmucsr0 instruction.
>
> Signed-off-by: Laurent Joye <laurent.joye at haslerrail.com>
> ---
> arch/powerpc/cpu/mpc85xx/tlb.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c
> b/arch/powerpc/cpu/mpc85xx/tlb.c
> index 929f6a6..c548f67 100644
> --- a/arch/powerpc/cpu/mpc85xx/tlb.c
> +++ b/arch/powerpc/cpu/mpc85xx/tlb.c
> @@ -38,6 +38,7 @@ void invalidate_tlb(u8 tlb)
> mtspr(MMUCSR0, 0x4);
> if (tlb == 1)
> mtspr(MMUCSR0, 0x2);
> + asm volatile("isync");
> }
>
> void init_tlbs(void)
>
We can probably just get rid of that function. It only affects
non-IPROT entries, of which we shouldn't have any. As of "powerpc/85xx:
clear out TLB on boot" we shouldn't have any stale TLB1 entries from
before U-Boot took over.
-Scott
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