[U-Boot] Cache alignment warnings on Tegra (ARM)
Marek Vasut
marex at denx.de
Tue Sep 18 23:20:30 CEST 2012
Dear Thierry Reding,
> On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
> > Dear Thierry Reding,
> >
> > [...]
> >
> > > > Sure, but after you apply the bounce buffer, you can safely
> > > > invalidate the whole cacheline, so align it up and be done with it.
> > >
> > > That's what I proposed to do last time around but it was NAK'ed.
> >
> > By who?
>
> I think it was Simon Glass and Mike Frysinger. They NAK'ed it for very
> valid reason, so I'm not complaining.
>
> > > At the
> > > time I didn't ensure that the buffer was actually big enough, which is
> > > why people didn't like it (data on the stack after the DMA buffer might
> > > be invalidated as well).
> >
> > Correct, thus the bounce buffer.
>
> I don't think we even need the bounce buffer. All that needs to be done
> is guarantee that the buffers passed to the MMC driver are properly
> aligned and sized.
If you resize the MMC structures and call sizeof() on them to get the size of
the transfer, the MMC won't work correctly anymore.
> Thierry
Best regards,
Marek Vasut
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