[U-Boot] Cache alignment warnings on Tegra (ARM)

[Marek Vasut]

Dear Simon Glass,

> Hi,
> 
> On Tue, Sep 18, 2012 at 1:04 PM, Thierry Reding
> 
> <thierry.reding at avionic-design.de> wrote:
> > On Tue, Sep 18, 2012 at 09:36:18PM +0200, Marek Vasut wrote:
> >> Dear Thierry Reding,
> >> 
> >> [...]
> >> 
> >> > > Sure, but after you apply the bounce buffer, you can safely
> >> > > invalidate the whole cacheline, so align it up and be done with it.
> >> > 
> >> > That's what I proposed to do last time around but it was NAK'ed.
> >> 
> >> By who?
> > 
> > I think it was Simon Glass and Mike Frysinger. They NAK'ed it for very
> > valid reason, so I'm not complaining.
> > 
> >> > At the
> >> > time I didn't ensure that the buffer was actually big enough, which is
> >> > why people didn't like it (data on the stack after the DMA buffer
> >> > might be invalidated as well).
> >> 
> >> Correct, thus the bounce buffer.
> > 
> > I don't think we even need the bounce buffer. All that needs to be done
> > is guarantee that the buffers passed to the MMC driver are properly
> > aligned and sized.
> > 
> > Thierry
> 
> Perhaps a point to make here is that we really don't want every driver
> (or even driver stack) implementing bounce buffers to when it is not a
> huge effort to change the code that calls them (typically filesystem
> code) to do the right thing. The code will be smaller and more
> efficient if the alignment issues are dealt with at source IMO.

You need the BB for user-case, when user gives you misaligned buffer.

Best regards,
Marek Vasut