[U-Boot] [RFC PATCH 16/17] powerpc/mpc85xx/p2020rdb-pc: fix SPL DDR config

[Scott Wood]

This is a temporary fix, and may not be appropriate for all revisions of
the board.  Presumably the original numbers worked for someone.  These
values are what the SPD code came up with on a P2020RDB-PCA.

The real solution is to have the SPL load into L2 cache, so that the main
U-Boot can use SPD.  I hope to implement that for the non-RFC version of
this patchset.  This makes the board work in the meantime, though.

Signed-off-by: Scott Wood <scottwood at freescale.com>
Cc: Andy Fleming <afleming at gmail.com>
---
 include/configs/p1_p2_rdb_pc.h |   20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index b3c4793..9d5383e 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -275,22 +275,22 @@
 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
 
 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8645F607
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8675f608
 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
 #define CONFIG_SYS_DDR_RCW_1		0x00000000
 #define CONFIG_SYS_DDR_RCW_2		0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xC7000000	/* Type = DDR3	*/
-#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_CONTROL		0xC7000008	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401040
 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
 #define CONFIG_SYS_DDR_TIMING_5		0x02401400
 
-#define CONFIG_SYS_DDR_TIMING_3		0x00020000
-#define CONFIG_SYS_DDR_TIMING_0		0x00330104
-#define CONFIG_SYS_DDR_TIMING_1		0x6f6B4644
-#define CONFIG_SYS_DDR_TIMING_2		0x0FA88CCF
-#define CONFIG_SYS_DDR_CLK_CTRL		0x02000000
-#define CONFIG_SYS_DDR_MODE_1		0x00421422
-#define CONFIG_SYS_DDR_MODE_2		0x04000000
+#define CONFIG_SYS_DDR_TIMING_3		0x00030000
+#define CONFIG_SYS_DDR_TIMING_0		0x00110104
+#define CONFIG_SYS_DDR_TIMING_1		0x6f6b8846
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa8c8cc
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
+#define CONFIG_SYS_DDR_MODE_1		0x00421421
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
 #define CONFIG_SYS_DDR_INTERVAL		0x0C300100
 
 #else
-- 
1.7.9.5