[U-Boot] [PATCH 2/3] FEC: Rework the TX wait mechanism

[Joe Hershberger]

Hi Marek,

On Wed, Aug 29, 2012 at 8:49 AM, Marek Vasut <marex at denx.de> wrote:
> The mechanism waiting for transmission to finish in fec_send() now
> relies on the E-bit being cleared in the TX buffer descriptor. In
> case of data cache being on, this means invalidation of data cache
> above this TX buffer descriptor on each test for the E-bit being
> cleared.
>
> Apparently, there is another way to check if the transmission did
> complete. This is by checking the TDAR bit in the X_DES_ACTIVE
> register. Reading a register does not need any data cache invalidation,
> which is beneficial.
>
> Rework the sequence that wait for completion of the transmission so that
> the TDAR bit is tested first and afterwards check the E-bit being clear.
> This cuts down the number of cache invalidation calls to one.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Joe Hershberger <joe.hershberger at ni.com>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Otavio Salvador <otavio at ossystems.com.br>
> Cc: Stefano Babic <sbabic at denx.de>
> ---

Applied, thanks.

-Joe