[U-Boot] [PATCH RFC 20/22] i.MX6: MX6Q: update MIPI_HSI_CTRL declarations to match MX6DL

[Eric Nelson]

Signed-off-by: Eric Nelson <eric.nelson at boundarydevices.com>
---
 arch/arm/include/asm/arch-mx6/mx6q_pins.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index efc7651..2e26452 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -41,21 +41,21 @@ enum {
 	MX6_PAD_RGMII_TXC__GPIO_6_19		= IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT	= IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	= IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD0__GPIO_6_20		= IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	= IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD1__GPIO_6_21		= IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD1__CCM_PLL3_BYP	= IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	= IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD2__GPIO_6_22		= IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD2__CCM_PLL2_BYP	= IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	= IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD3__GPIO_6_23		= IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
@@ -63,7 +63,7 @@ enum {
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	= IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
 	MX6_PAD_RGMII_RX_CTL__GPIO_6_24	= IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5	= IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0      = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
 	MX6_PAD_RGMII_RD0__GPIO_6_25		= IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
@@ -72,16 +72,16 @@ enum {
 	MX6_PAD_RGMII_TX_CTL__GPIO_6_26	= IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7	= IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
 	MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT	= IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
-	MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	= IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
 	MX6_PAD_RGMII_RD1__GPIO_6_27		= IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD1__SJC_FAIL		= IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	= IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
 	MX6_PAD_RGMII_RD2__GPIO_6_28		= IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
-	MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
+	MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	= IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0),
 	MX6_PAD_RGMII_RD3__GPIO_6_29		= IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
 	MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
-- 
1.8.1.2