[U-Boot] [PATCH] powerpc/mpc85xx: Add support for single source clocking

[Priyanka.Jain at freescale.com]

> -----Original Message-----
> From: Jain Priyanka-B32167
> Sent: Monday, December 09, 2013 2:59 PM
> To: Sun York-R58495
> Cc: Aggrwal Poonam-B10812; Jain Priyanka-B32167; u-boot at lists.denx.de
> Subject: RE: [PATCH] powerpc/mpc85xx: Add support for single source
> clocking
> 
> Hello York,
> 
> I am not able to find mail which contains your comment on to undefined
> CONFIG_DDR_CLK_FREQ, so replying on original mail.
> 
> ----
> You are right that we don't need to define CONFIG_DDR_CLK_FREQ in case of
> single source clocking.
> But as T1040QDS supports both single source clocking and separate
> clocking (for DDR and sysclk) and we intend to keep single u-boot binary
> for both modes, we need a mechanism to decide clocking mode at runtime.
> We thought of implementing it via rcw bit. Please suggest if there is
> some other good way to do so.
> 
> Thanks
> Priyanka
> 
> 
> 
> 
> > -----Original Message-----
> > From: Jain Priyanka-B32167
> > Sent: Thursday, November 28, 2013 11:05 AM
> > To: u-boot at lists.denx.de
> > Cc: Sun York-R58495; Jain Priyanka-B32167; Aggrwal Poonam-B10812
> > Subject: [PATCH] powerpc/mpc85xx: Add support for single source
> > clocking
> >
> > Single-source clocking is new feature introduced in T1040.
> > In this mode, a differential clock is supplied to the DIFF_SYSCLK_P/N
> > inputs to the processor, which in turn is used to supply clocks to the
> > sysclock, ddrclock and usbclock.
> >
> > So, both ddrclock and syclock are driven by same differential sysclock
> > in single-sourec clocking whereas in normal clocking mode, generally
> > separate DDRCLK and SYSCLK pins provides reference clock for sysclock
> > and ddrclock
> >
> > DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If
> > DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in  normal
> > clocking mode by DDR_Reference clock
> >
> > -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in  single
> > source clocking mode by DIFF_SYSCLK
> >
> > Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
> >
> > Signed-off-by: Poonam Aggrwal <poonam.aggrwal at freescale.com>
> > Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com>
> > ---
> >  arch/powerpc/cpu/mpc85xx/speed.c          |   20 ++++++++++++++++++++
> >  arch/powerpc/include/asm/config_mpc85xx.h |    1 +
> >  arch/powerpc/include/asm/immap_85xx.h     |    3 +++
> >  3 files changed, 24 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/powerpc/cpu/mpc85xx/speed.c
> > b/arch/powerpc/cpu/mpc85xx/speed.c
> > index 1a58a19..cd49695 100644
> > --- a/arch/powerpc/cpu/mpc85xx/speed.c
> > +++ b/arch/powerpc/cpu/mpc85xx/speed.c
> > @@ -77,7 +77,27 @@ void get_sys_info(sys_info_t *sys_info)
> >
> >  	sys_info->freq_systembus = sysclk;
> >  #ifdef CONFIG_DDR_CLK_FREQ
> > +#ifdef CONFIG_SINGLE_SOURCE_CLK
> > +	/*
> > +	 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
> > +	 * are driven by separate DDR Refclock or single source
> > +	 * differential clock.
> > +	 */
> > +	uint single_src;
> > +	single_src = (in_be32(&gur->rcwsr[5]) >>
> > +		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
> > +		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
> > +	/*
> > +	 * For single source clocking, both ddrclock and syclock
> > +	 * are driven by differential sysclock.
> > +	 */
> > +	if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
> > +		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
> > +	else
> > +		sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else
> >  	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
> > +#endif
> >  #else
> >  	sys_info->freq_ddrbus = sysclk;
> >  #endif
> > diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
> > b/arch/powerpc/include/asm/config_mpc85xx.h
> > index 99e16bd..370bd21 100644
> > --- a/arch/powerpc/include/asm/config_mpc85xx.h
> > +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> > @@ -711,6 +711,7 @@ defined(CONFIG_PPC_T1020) ||
> > defined(CONFIG_PPC_T1022)
> >  #define CONFIG_FM_PLAT_CLK_DIV	1
> >  #define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
> >  #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
> > +#define CONFIG_SINGLE_SOURCE_CLK
> >  #define CONFIG_SYS_FSL_TBCLK_DIV	32
> >  #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
> >  #define CONFIG_SYS_FSL_USB1_PHY_ENABLE diff --git
> > a/arch/powerpc/include/asm/immap_85xx.h
> > b/arch/powerpc/include/asm/immap_85xx.h
> > index 672e8c6..68c3c82 100644
> > --- a/arch/powerpc/include/asm/immap_85xx.h
> > +++ b/arch/powerpc/include/asm/immap_85xx.h
> > @@ -1774,6 +1774,9 @@ defined(CONFIG_PPC_T1020) ||
> > defined(CONFIG_PPC_T1022)
> >  #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2	0x00040000
> >  #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1	0x00020000
> >  #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2	0x00010000
> > +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
> > +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK	0x00000011
> > +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK	1
> >
> >  #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
> >  #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
> > --
> > 1.7.4.1
> >