[U-Boot] [PATCH 2/4] arm: lager: Add support Ethernet

[Nobuhiro Iwamatsu]

From: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>

The lager board has one sh-ether device.
This supports sh-ether.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
---
 board/renesas/lager/lager.c | 70 +++++++++++++++++++++++++++++++++++++++++++++
 include/configs/lager.h     | 21 +++++++++++++-
 2 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 5c99fc9..8447fe1 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <netdev.h>
+#include <miiphy.h>
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
@@ -207,6 +208,10 @@ void s_init(void)
 #define SMSTPCR7	0xE615014C
 #define SCIF0_MSTP721	(1 << 21)
 
+#define MSTPSR8	0xE61509A0
+#define SMSTPCR8	0xE6150990
+#define ETHER_MSTP813	(1 << 13)
+
 #define PMMR	0xE6060000
 #define GPSR4	0xE6060014
 #define IPSR14	0xE6060058
@@ -242,6 +247,9 @@ int board_early_init_f(void)
 
 	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
 
+	/* Ether */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
 	return 0;
 }
 
@@ -256,6 +264,68 @@ int board_init(void)
 	/* Init PFC controller */
 	r8a7790_pinmux_init();
 
+	/* Ether Enable */
+	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+	gpio_request(GPIO_FN_ETH_RXD0, NULL);
+	gpio_request(GPIO_FN_ETH_RXD1, NULL);
+	gpio_request(GPIO_FN_ETH_LINK, NULL);
+	gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
+	gpio_request(GPIO_FN_ETH_MDIO, NULL);
+	gpio_request(GPIO_FN_ETH_TXD1, NULL);
+	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+	gpio_request(GPIO_FN_ETH_TXD0, NULL);
+	gpio_request(GPIO_FN_ETH_MDC, NULL);
+	gpio_request(GPIO_FN_IRQ0, NULL);
+
+	gpio_request(GPIO_GP_5_31, NULL);	/* PHY_RST */
+	gpio_direction_output(GPIO_GP_5_31, 0);
+	mdelay(20);
+	gpio_set_value(GPIO_GP_5_31, 1);
+	udelay(1);
+
+	return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+	int ret = -ENODEV;
+	u32 val;
+	unsigned char enetaddr[6];
+
+	ret = sh_eth_initialize(bis);
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		return ret;
+
+	/* Set Mac address */
+	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+	    enetaddr[2] << 8 | enetaddr[3];
+	writel(val, CXR24);
+
+	val = enetaddr[4] << 8 | enetaddr[5];
+	writel(val, CXR25);
+
+	return ret;
+#else
+	return 0;
+#endif
+}
+
+/* lager has KSZ8041NL/RNL */
+#define PHY_CONTROL1	0x1E
+#define PHY_LED_MODE	0xC0000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
 	return 0;
 }
 
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 7819edd..0dc9b6e 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -28,8 +28,13 @@
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
 #define CONFIG_CMD_BOOTZ
-#define	CONFIG_CMD_FLASH
+#define CONFIG_CMD_FLASH
 
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
@@ -127,6 +132,20 @@
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
 
+/* SH Ether */
+#define CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
 /* Board Clock */
 #define CONFIG_BASE_CLK_FREQ	20000000u
 #define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
-- 
1.8.5