[U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL

[Scott Wood]

On Wed, 2013-12-11 at 12:10 +0530, Prabhakar Kushwaha wrote:
> On 12/10/2013 11:50 PM, Scott Wood wrote:
> > On Tue, 2013-12-10 at 11:37 +0530, Prabhakar Kushwaha wrote:
> >> On 12/9/2013 11:21 PM, Scott Wood wrote:
> >>> On Mon, 2013-12-09 at 11:10 +0530, Prabhakar Kushwaha wrote:
> >>>> On 12/7/2013 6:51 AM, Scott Wood wrote:
> >>>>> Prabhakar, why did you extend that to other uses?  Why are both entries
> >>>>> ifdeffed here, but only the 0xffffe000 entry on existing boards?
> >>>> both entry should not be in ifdef. p1010rdb/bsc9131rdb/bsc9132qds does
> >>>> not have this.
> >>>> i dont think NOR boot tested after this patch. NOR boot will not work
> >>>> after applying this patch.
> >>> So what happens if there's a speculative access to the non-ifdeffed
> >>> 0xfffff000 when we're not booting from that (e.g. ramboot, SPL payload,
> >>> SD/SPI...)?
> >>>
> >>>
> >> If I understand the question correctly,
> >>      Ideally ramboot, SPL payload, SD/SPI should not make access to this
> >> address.  They assumed to be running from DDR whose TLB has already been
> >> created by IBR, or First stage boot loader.
> > Speculative accesses don't come (directly) from software.  They are
> > initiated by the hardware and are not predictable.
> >
> >
> 
> Please help me in understanding this.
>    What are the scenario where it is possible? means how hardware can 
> initiate any access?
>    do hardware initiated transaction require TLB?

Any mapping that is in the TLB can be used for speculative reads (except
that the guarded bit or lack of read permission inhibits speculative
data reads, and the lack of execute permission inhibits speculative
instruction fetches).  Any TLB where speculative reads aren't inhibited
as described must be backed by something memory-like.

The CPU will do this when it predicts that it will need data from that
address, though sometimes the predictions are wrong.

-Scott