[U-Boot] [PATCH] board/t1040qds: Relax IFC FPGA timings

[Prabhakar Kushwaha]

Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
freqencies.

So, Increase TCH as 0x8 i.e. 8 ip_clk.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
 include/configs/T1040QDS.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 74f4bde..521a0dc 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -247,7 +247,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
-- 
1.7.9.5