[U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL

[Scott Wood]

On Wed, 2013-12-11 at 00:16 -0600, Liu Po-B43644 wrote:
> >  >  	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
> >  > -			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> >  > +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> >  >  			0, 5, BOOKE_PAGESZ_64K, 1),
> >  
> >  No.
> Without MAS3_SX, the board can't run in booting from NAND. 

Explain why you're executing from this TLB entry.  This should be for
accessing the NAND as I/O after you've relocated away from the boot
buffer.  There should be a different mapping for the boot buffer early
on.  None of the other NAND boot targets have needed this.  Perhaps this
is related to the other TLB entry that you said you could work without.

> >  >  	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, @@ -61,7 +72,8 @@
> >  > struct fsl_e_tlb_entry tlb_table[] = {
> >  >  			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> >  >  			0, 7, BOOKE_PAGESZ_256K, 1),
> >  >
> >  > -#ifdef CONFIG_SYS_RAMBOOT
> >  > +#if defined(CONFIG_SYS_RAMBOOT) || (defined(CONFIG_SPL) \
> >  > +		&& !defined(CONFIG_SPL_COMMON_INIT_DDR))
> >  >  	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
> >  >  			CONFIG_SYS_DDR_SDRAM_BASE,
> >  >  			MAS3_SX|MAS3_SW|MAS3_SR, 0,
> >  
> >  This will have the result of mapping DDR in the SPL where it's not used,
> >  but not in the TPL where it is.
> For the TPL the ddr initial by initdram(), so don't need to mapping ddr here. 
> I intend to change it to #if defined(CONFIG_SYS_RAMBOOT) || !defined(CONFIG_SPL_COMMON_INIT_DDR)
> Is it more clear?

No, you'll still end up mapping it in the SPL (when DDR hasn't been set
up yet, so again there could be speculative accesses causing machine
checks), and that change would make the mapping happen in ordinary NOR
boot as well (where it would duplicate what initdram() does).  We only
want this TLB entry in phases that are booting out of DDR.

How about:
#if defined(CONFIG_SYS_RAMBOOT) || \
	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))

...with the assumption that all SPLs for a given board will either put
the final U-boot in DDR or SRAM, and the board tlb.c knows the
difference.

-Scott