[U-Boot] [PATCH v2 26/35] zynq: Add support to find bootmode
Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-teki at xilinx.com
Wed Dec 18 16:30:11 CET 2013
Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.
Added this functionality on board_late_init as it's not
needed for normal initializtion part.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna at xilinx.com>
---
V2: none
arch/arm/cpu/armv7/zynq/slcr.c | 6 ++++++
arch/arm/include/asm/arch-zynq/sys_proto.h | 1 +
board/xilinx/zynq/board.c | 33 ++++++++++++++++++++++++++++++
doc/README.zynq | 27 ++++++++++++++++++++++--
include/configs/zynq-common.h | 1 +
5 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 717ec65..b4c11c3 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -101,6 +101,12 @@ void zynq_slcr_devcfg_enable(void)
zynq_slcr_lock();
}
+u32 zynq_slcr_get_boot_mode(void)
+{
+ /* Get the bootmode register value */
+ return readl(&slcr_base->boot_mode);
+}
+
u32 zynq_slcr_get_idcode(void)
{
return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 110de90..8f925af 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -13,6 +13,7 @@ extern void zynq_slcr_cpu_reset(void);
extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_boot_mode(void);
extern u32 zynq_slcr_get_idcode(void);
extern void zynq_ddrc_init(void);
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 5119c09..118db3a 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -12,6 +12,14 @@
DECLARE_GLOBAL_DATA_PTR;
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK 0x0F
+#define ZYNQ_BM_QSPI 0x01
+#define ZYNQ_BM_NOR 0x02
+#define ZYNQ_BM_NAND 0x04
+#define ZYNQ_BM_SD 0x05
+#define ZYNQ_BM_JTAG 0x0
+
#ifdef CONFIG_FPGA
Xilinx_desc fpga;
@@ -59,6 +67,31 @@ int board_init(void)
return 0;
}
+int board_late_init(void)
+{
+ switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+ case ZYNQ_BM_QSPI:
+ setenv("modeboot", "qspiboot");
+ break;
+ case ZYNQ_BM_NOR:
+ setenv("modeboot", "norboot");
+ break;
+ case ZYNQ_BM_NAND:
+ setenv("modeboot", "nandboot");
+ break;
+ case ZYNQ_BM_SD:
+ setenv("modeboot", "sdboot");
+ break;
+ case ZYNQ_BM_JTAG:
+ setenv("modeboot", "jtagboot");
+ break;
+ default:
+ setenv("modeboot", "");
+ break;
+ }
+
+ return 0;
+}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
diff --git a/doc/README.zynq b/doc/README.zynq
index 56a74b4..7cb87e3 100644
--- a/doc/README.zynq
+++ b/doc/README.zynq
@@ -28,7 +28,29 @@ and I/O programmability.
- zc770-xm012 (nor)
- zc770-xm013 (dual parallel qspi, gem1)
-3. Mainline status
+3. Bootmode
+
+Zynq has a facility to read the bootmode from the slcr bootmode register
+once user is setting through jumpers on the board - see page no:1546 on [5]
+
+All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins
+on [5].
+
+board_late_init() will read the bootmode values using slcr bootmode register
+at runtime and assign the modeboot variable to specific bootmode string which
+is intern used in autoboot.
+
+SLCR bootmode register Bit[3:0] values
+#define ZYNQ_BM_QSPI 0x01
+#define ZYNQ_BM_NOR 0x02
+#define ZYNQ_BM_NAND 0x04
+#define ZYNQ_BM_SD 0x05
+#define ZYNQ_BM_JTAG 0x0
+
+"modeboot" variable can assign any of "qspiboot", "norboot", "nandboot",
+"sdboot" or "jtagboot" bootmode strings at runtime.
+
+4. Mainline status
- Added basic board configurations support.
- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
@@ -41,7 +63,7 @@ and I/O programmability.
spi- drivers/spi/zynq_spi.c
i2c - drivers/i2c/zynq_i2c.c
-4. TODO
+5. TODO
- Add zynq boards support - zc70x, zed, microzed, zc770
- Add zynq qspi controller driver
@@ -54,6 +76,7 @@ and I/O programmability.
[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
[3] http://zedboard.org/product/zedboard
[4] http://zedboard.org/product/microzed
+[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
--
Jagannadha Sutradharudu Teki <jaganna at xilinx.com>
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index bb615d0..676ff12 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -161,6 +161,7 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
--
1.8.3
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