[U-Boot] [PATCH] board/t1040qds: Add memory reset control

[Prabhakar Kushwaha]

 JEDEC spec requires the clocks to be stable before deasserting reset
 signal for RDIMMs. Clocks start when any chip select is enabled and
 clock control register is set. This patch also adds the interface to
 toggle memory reset signal if needed by the boards.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
 board/freescale/t1040qds/t1040qds.c |    5 +++++
 include/configs/T1040QDS.h          |    1 +
 2 files changed, 6 insertions(+)

diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 2aa176c..de3ea5c 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -239,3 +239,8 @@ void qixis_dump_switch(void)
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
 }
+
+int board_need_mem_reset(void)
+{
+	return 1;
+}
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 1cfbf06..7bae2c8 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -232,6 +232,7 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
 
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
-- 
1.7.9.5