[U-Boot] [PATCH] Origen: Correct equation to calculate PLL output frequency

[Rajeshwari Shinde]

EXYNOS4 user manual equation for calculating PLL output is
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
hence updating accordingly.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s at samsung.com>
---
 arch/arm/cpu/armv7/exynos/clock.c |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index e1c4246..af0fa5b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -116,8 +116,15 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 		/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
 		fout = (m + k / 1024) * (freq / (p * (1 << s)));
 	} else {
-		/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
-		fout = m * (freq / (p * (1 << s)));
+		if (cpu_is_exynos4()) {
+			if (s < 1)
+				s = 1;
+			/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+			fout = m * (freq / (p * (1 << (s - 1))));
+		} else {
+			/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+			fout = m * (freq / (p * (1 << s)));
+		}
 	}
 
 	return fout;
-- 
1.7.4.4