[U-Boot] [PATCH v6 02/12] video: add Faraday FTLCDC200 LCD controller support
Kuo-Jung Su
dantesu at gmail.com
Thu Jul 4 05:40:34 CEST 2013
From: Kuo-Jung Su <dantesu at faraday-tech.com>
Faraday FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray or color value
2. an address to a 256 x 16 bit wide palette RAM gray or color value.
The FTLCDC200 generates 4 individual interrupts for:
1. DMA FIFO underflow
2. base address update
3. vertical status
4. bus error.
There is also a single combined interrupt that is raised when any of
the individual interrupts become active.
Signed-off-by: Kuo-Jung Su <dantesu at faraday-tech.com>
CC: Albert Aribaud <albert.u.boot at aribaud.net>
CC: Anatolij Gustschin <agust at denx.de>
---
Changes for v6:
- Nothing updates
Changes for v5:
- Coding Style cleanup:
struct chip_regs __iomem *regs -> struct chip_regs *regs
- Chain it back to Faraday A360/A369 patch series, because
Faraday A369 depends on the header file of this patch
for I2C work-around.(Enable I2C clock to prevent I2C bus hangs)
Changes for v4:
- Nothing updates
Changes for v3:
- Nothing updates
Changes for v2:
- Make it a separate patch, rather then a part of
Faraday A36x patch series
drivers/video/Makefile | 1 +
drivers/video/ftlcdc200.c | 148 ++++++++++++++++++++++++++
drivers/video/ftlcdc200_panel.c | 221 +++++++++++++++++++++++++++++++++++++++
include/faraday/ftlcdc200.h | 179 +++++++++++++++++++++++++++++++
include/lcd.h | 33 ++++++
5 files changed, 582 insertions(+)
create mode 100644 drivers/video/ftlcdc200.c
create mode 100644 drivers/video/ftlcdc200_panel.c
create mode 100644 include/faraday/ftlcdc200.h
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 68ff34b..92ab9d1 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
exynos_mipi_dsi_lowlevel.o
COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
+COBJS-$(CONFIG_FTLCDC200) += ftlcdc200.o ftlcdc200_panel.o
COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o
COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
diff --git a/drivers/video/ftlcdc200.c b/drivers/video/ftlcdc200.c
new file mode 100644
index 0000000..331a35f
--- /dev/null
+++ b/drivers/video/ftlcdc200.c
@@ -0,0 +1,148 @@
+/*
+ * Faraday LCD Controller
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu at faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <lcd.h>
+#include <faraday/ftlcdc200.h>
+
+#ifndef CONFIG_FTLCDC200_FREQ
+#define CONFIG_FTLCDC200_FREQ clock_get_rate(AHB_CLK)
+#endif
+
+static struct ftlcdc200_regs *regs = (void __iomem *)CONFIG_FTLCDC200_BASE;
+
+static void ftlcdc2xx_fixup(struct vidinfo *panel)
+{
+ u_long ht, vt;
+ u_long div, clk;
+ long fps = 60;
+ long upper = 32767;
+ long lower = -32767;
+
+ if (panel->vl_fps)
+ return;
+
+ /* If it's serial mode */
+ if (panel->vl_serial & SPPR_SERIAL)
+ clk = CONFIG_FTLCDC200_FREQ / 3;
+ else
+ clk = CONFIG_FTLCDC200_FREQ;
+
+ /* Derive clock divisor */
+ ht = panel->vl_col + panel->vl_hbp + panel->vl_hfp + panel->vl_hsw;
+ vt = panel->vl_row + panel->vl_vbp + panel->vl_vfp + panel->vl_vsw;
+ for (div = 1; div <= 0x7f; ++div) {
+ long tmp = (clk / div / ht / vt);
+ if (fps > tmp) {
+ lower = tmp;
+ break;
+ }
+ upper = tmp;
+ }
+ if ((upper - fps) > (fps - lower))
+ div += 1;
+ div = (div > 1) ? (div - 1) : div;
+
+ /* Update hardware register cache */
+ panel->vl_polarity = (panel->vl_polarity & (~0x7f00))
+ | ((div - 1) << 8);
+
+ /* Derive real frame rate */
+ panel->vl_fps = (u_long)(clk / div / ht / vt);
+
+ debug("ftlcdc200: %s\n", panel->vl_name);
+ debug("ftlcdc200: fps=%u (%u < FPS < %u)\n",
+ (unsigned int)panel->vl_fps,
+ (unsigned int)lower,
+ (unsigned int)upper);
+ debug("ftlcdc200: div=%u (ahb=%u MHz)\n",
+ (unsigned int)div,
+ (unsigned int)CONFIG_FTLCDC200_FREQ / 1000000);
+}
+
+/* setcolreg used in 8bpp/16bpp */
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+ /* nothing needs to be done, we use true color */
+}
+
+/* initcolregs used in monochrome */
+void lcd_initcolregs(void)
+{
+ /* nothing needs to be done, we use true color */
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ uint32_t i, v;
+
+ /*
+ * initialize the contrast lookup table and the Red, Green, Blue
+ * gamma lookup table, fill the straight line x-y=0 to the contrast
+ * and gamma lookup table
+ */
+ for (i = 0; i < 64; i++) {
+ v = 0x03020100 + 0x04040404 * i;
+ writel(v, ®s->gamma_r[i]);
+ writel(v, ®s->gamma_g[i]);
+ writel(v, ®s->gamma_b[i]);
+ }
+
+ writel(virt_to_phys(lcdbase), ®s->fb0);
+
+ debug("ftlcdc200: fb_base=0x%08X at 0x%08X\n",
+ (uint32_t)lcdbase, readl(®s->fb0));
+}
+
+void lcd_enable(void)
+{
+ struct vidinfo *panel = &panel_info;
+
+ /* 1. derive the clock parameters at runtime */
+ ftlcdc2xx_fixup(panel);
+ /* 2. disable lcd */
+ writel(0, ®s->fer);
+ /* 3. setup panel parameters */
+ writel(panel->vl_pixel, ®s->ppr);
+ writel(HTCR_PL(panel->vl_col) | HTCR_HSYNC(panel->vl_hsw)
+ | HTCR_HBP(panel->vl_hbp) | HTCR_HFP(panel->vl_hfp),
+ ®s->htcr);
+ writel(VTCR0_LF(panel->vl_row) | VTCR0_VSYNC(panel->vl_vsw)
+ | VTCR0_VFP(panel->vl_vfp), ®s->vtcr[0]);
+ writel(VTCR1_VBP(panel->vl_vbp), ®s->vtcr[1]);
+ writel(panel->vl_polarity, ®s->pcr);
+ writel(panel->vl_serial, ®s->sppr);
+ writel(panel->vl_ccir656, ®s->ccir);
+ /* 4. default 4 cycles delay for all framebuffer */
+ writel(0x04040404, ®s->fifo);
+ /* 5. disable & clean interrupts */
+ writel(0x00, ®s->ier);
+ writel(0x0f, ®s->iscr);
+ /* 6. enable lcd */
+ writel(panel->vl_enable, ®s->fer);
+}
+
+ulong calc_fbsize(void)
+{
+ return ((panel_info.vl_col * panel_info.vl_row *
+ NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
+}
diff --git a/drivers/video/ftlcdc200_panel.c b/drivers/video/ftlcdc200_panel.c
new file mode 100644
index 0000000..43b38c7
--- /dev/null
+++ b/drivers/video/ftlcdc200_panel.c
@@ -0,0 +1,221 @@
+/*
+ * Faraday LCD Controller
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu at faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <lcd.h>
+#include <faraday/ftlcdc200.h>
+
+struct vidinfo panel_info = {
+#if defined(CONFIG_FTLCDC200_320X240P_SHARP)
+ .vl_name = "SHARP-320x240p",
+ .vl_col = 320,
+ .vl_row = 240,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 0, /* drived at runtime */
+ .vl_hsw = 0x10,
+ .vl_hfp = 0x01,
+ .vl_hbp = 0x10,
+ .vl_vsw = 0x01,
+ .vl_vfp = 0x0f,
+ .vl_vbp = 0x07,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_BGR | PPR_ENDIAN_LBLP,
+ .vl_polarity = POL_DIV(23) | POL_IHS | POL_ICK,
+ .vl_serial = 0,
+ .vl_ccir656 = 0,
+#elif defined(CONFIG_FTLCDC200_320X240P_AUO)
+ .vl_name = "AUO-320x240p",
+ .vl_col = 320,
+ .vl_row = 240,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 0, /* drived at runtime */
+ .vl_hsw = 0x17,
+ .vl_hfp = 0x01,
+ .vl_hbp = 0x2A,
+ .vl_vsw = 0x01,
+ .vl_vfp = 0x01,
+ .vl_vbp = 0x0D,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_PWROFF,
+ .vl_polarity = POL_DIV(21) | POL_IHS,
+ .vl_serial = 0,
+ .vl_ccir656 = 0,
+#elif defined(CONFIG_FTLCDC200_320X240S_AUO)
+ .vl_name = "AUO-320x240s",
+ .vl_col = 320,
+ .vl_row = 240,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 0, /* drived at runtime */
+ .vl_hsw = 0x17,
+ .vl_hfp = 0x01,
+ .vl_hbp = 0x2A,
+ .vl_vsw = 0x01,
+ .vl_vfp = 0x01,
+ .vl_vbp = 0x0D,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_PANEL_8BIT
+ | PPR_ENDIAN_LBBP,
+ .vl_polarity = POL_DIV(7) | POL_IHS,
+ .vl_serial = SPPR_SERIAL | SPPR_CS(1),
+ .vl_ccir656 = 0,
+#elif defined(CONFIG_FTLCDC200_640X480P_PV)
+ .vl_name = "PV-640x480p",
+ .vl_col = 640,
+ .vl_row = 480,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 0, /* drived at runtime */
+ .vl_hsw = 0x63,
+ .vl_hfp = 0x01,
+ .vl_hbp = 0x2D,
+ .vl_vsw = 0x44,
+ .vl_vfp = 0x01,
+ .vl_vbp = 0x1D,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_BGR | PPR_ENDIAN_LBBP,
+ .vl_polarity = POL_DIV(6) | POL_IHS | POL_IVS | POL_ICK,
+ .vl_serial = 0,
+ .vl_ccir656 = 0,
+#elif defined(CONFIG_FTLCDC200_800X480S_TPO)
+ .vl_name = "TPO-800x480s",
+ .vl_col = 800,
+ .vl_row = 480,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 0, /* drived at runtime */
+ .vl_hsw = 0x01,
+ .vl_hfp = 0x2C,
+ .vl_hbp = 0x01,
+ .vl_vsw = 0x01,
+ .vl_vfp = 0x01,
+ .vl_vbp = 0x01,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_ENDIAN_LBBP,
+ .vl_polarity = POL_DIV(1) | POL_IHS | POL_IVS | POL_ICK,
+ .vl_serial = SPPR_SERIAL | SPPR_CS(0),
+ .vl_ccir656 = 0,
+#elif defined(CONFIG_FTLCDC200_800X480P_TPO)
+ .vl_name = "TPO-800x480p",
+ .vl_col = 800,
+ .vl_row = 480,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 0, /* drived at runtime */
+ .vl_hsw = 0x04,
+ .vl_hfp = 0x2C,
+ .vl_hbp = 0xD4,
+ .vl_vsw = 0x02,
+ .vl_vfp = 0x0A,
+ .vl_vbp = 0x22,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_BGR | PPR_ENDIAN_LBBP,
+ .vl_polarity = POL_DIV(7) | POL_IHS | POL_IVS | POL_ICK,
+ .vl_serial = 0,
+ .vl_ccir656 = 0,
+#elif defined(CONFIG_FTLCDC200_800X480P_CPT)
+ /* Chunghwa Picture Tubes - CLAA048LA0BCT */
+ .vl_name = "CPT-800x480p",
+ .vl_col = 800,
+ .vl_row = 480,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 0, /* drived at runtime */
+ .vl_hsw = 0x01,
+ .vl_hfp = 0x32,
+ .vl_hbp = 0x31,
+ .vl_vsw = 0x01,
+ .vl_vfp = 0x0E,
+ .vl_vbp = 0x05,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_PANEL_8BIT
+ | PPR_ENDIAN_LBBP,
+ .vl_polarity = POL_DIV(7) | POL_IHS | POL_IVS | POL_ICK,
+ .vl_serial = 0,
+ .vl_ccir656 = 0,
+#elif defined(CONFIG_FTLCDC200_800X600_VGA)
+ .vl_name = "D-SUB: VGA-800x600",
+ .vl_col = 800,
+ .vl_row = 600,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 0, /* drived at runtime */
+ .vl_hsw = 0x7E,
+ .vl_hfp = 0x26,
+ .vl_hbp = 0x56,
+ .vl_vsw = 0x02,
+ .vl_vfp = 0x01,
+ .vl_vbp = 0x16,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_PANEL_8BIT | PPR_BPP_16,
+ .vl_polarity = POL_DIV(3) | POL_IVS | POL_IHS,
+ .vl_serial = 0,
+ .vl_ccir656 = 0,
+#elif defined(CONFIG_FTLCDC200_1024X768_VGA)
+ .vl_name = "D-SUB: VGA-1024x768",
+ .vl_col = 1024,
+ .vl_row = 768,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 0, /* drived at runtime */
+ .vl_hsw = 0x7E,
+ .vl_hfp = 0x26,
+ .vl_hbp = 0x56,
+ .vl_vsw = 0x02,
+ .vl_vfp = 0x01,
+ .vl_vbp = 0x16,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_PANEL_8BIT | PPR_BPP_16,
+ .vl_polarity = POL_DIV(2) | POL_IVS | POL_IHS,
+ .vl_serial = 0,
+ .vl_ccir656 = 0,
+#elif defined(CONFIG_FTLCDC200_720X480_NTSC)
+ .vl_name = "A/V: NTSC-720x480",
+ .vl_col = 720,
+ .vl_row = 480,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 30, /* Frame per second */
+ .vl_hsw = 0x06,
+ .vl_hfp = 0x7D,
+ .vl_hbp = 0x01,
+ .vl_vsw = 0x0F,
+ .vl_vfp = 0x01,
+ .vl_vbp = 0x1A,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_ENDIAN_LBBP,
+ .vl_polarity = 0,
+ .vl_serial = 0,
+ .vl_ccir656 = 3,
+#elif defined(CONFIG_FTLCDC200_640X480_NTSC)
+ .vl_name = "A/V: NTSC-640x480",
+ .vl_col = 640,
+ .vl_row = 480,
+ .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */
+ .vl_fps = 30, /* Frame per second */
+ .vl_hsw = 0x02,
+ .vl_hfp = 0xD1,
+ .vl_hbp = 0x01,
+ .vl_vsw = 0x10,
+ .vl_vfp = 0x01,
+ .vl_vbp = 0x19,
+ .vl_enable = FER_EN | FER_ON,
+ .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_ENDIAN_LBBP,
+ .vl_polarity = 0,
+ .vl_serial = 0,
+ .vl_ccir656 = 1,
+#else
+#error "Please specific target LCD panel."
+#endif
+};
diff --git a/include/faraday/ftlcdc200.h b/include/faraday/ftlcdc200.h
new file mode 100644
index 0000000..35f19b7
--- /dev/null
+++ b/include/faraday/ftlcdc200.h
@@ -0,0 +1,179 @@
+/*
+ * Faraday LCD Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu at faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef __FTLCDC200_H
+#define __FTLCDC200_H
+
+/* FTLCDC200 Registers */
+struct ftlcdc200_regs {
+ /* 0x000 ~ 0x0ff */
+ uint32_t fer; /* 0x000: Function Enable Register */
+ uint32_t ppr; /* 0x004: Panel Pixel Register */
+ uint32_t ier; /* 0x008: Interrupt Enable Register */
+ uint32_t iscr; /* 0x00C: Interrupt Status Clear Register */
+ uint32_t isr; /* 0x010: Interrupt Status Register */
+ uint32_t rsvd0[1];
+ uint32_t fb0; /* 0x018: Framebuffer Base Register 0 */
+ uint32_t rsvd1[2];
+ uint32_t fb1; /* 0x024: Framebuffer Base Register 1 */
+ uint32_t rsvd2[2];
+ uint32_t fb2; /* 0x030: Framebuffer Base Register 2 */
+ uint32_t rsvd3[2];
+ uint32_t fb3; /* 0x03C: Framebuffer Base Register 3 */
+ uint32_t rsvd4[2];
+ uint32_t patg; /* 0x048: Pattern Generator */
+ uint32_t fifo; /* 0x04C: FIFO Threshold */
+ uint32_t gpio; /* 0x050: GPIO */
+ uint32_t rsvd5[43];
+
+ /* 0x100 ~ 0x1ff */
+ uint32_t htcr; /* Horizontal Timing Control Register */
+ uint32_t vtcr[2]; /* Vertical Timing Control Register */
+ uint32_t pcr; /* Polarity Control Register */
+ uint32_t rsvd6[60];
+
+ /* 0x200 ~ 0x2ff */
+ uint32_t sppr; /* Serial Panel Pixel Register */
+ uint32_t ccir; /* CCIR565 Register */
+ uint32_t rsvd7[62];
+
+ /* 0x300 ~ 0x3ff */
+ uint32_t pipr; /* Picture-In-Picture Register */
+ uint32_t pip1pos; /* Sub-picture 1 position */
+ uint32_t pip1dim; /* Sub-picture 1 dimension */
+ uint32_t pip2pos; /* Sub-picture 2 position */
+ uint32_t pip2dim; /* Sub-picture 2 dimension */
+ uint32_t rsvd8[59];
+
+ /* 0x400 ~ 0x5ff */
+ uint32_t cmnt[4]; /* Color Management */
+ uint32_t rsvd9[124];
+
+ /* 0x600 ~ 0x6ff */
+ uint32_t gamma_r[64]; /* RED - Gamma Correct */
+
+ /* 0x700 ~ 0x7ff */
+ uint32_t gamma_g[64]; /* GREEN - Gamma Correct */
+
+ /* 0x800 ~ 0x8ff */
+ uint32_t gamma_b[64]; /* BLUE - Gamma Correct */
+
+ /* 0x900 ~ 0x9ff */
+ uint32_t rsvd10[64];
+
+ /* 0xa00 ~ 0xbff */
+ uint32_t palette[128]; /* Palette Write Port */
+
+ /* 0xc00 ~ 0xcff */
+ uint32_t cstn_cr; /* CSTN Control Register */
+ uint32_t cstn_pr; /* CSTN Parameter Register */
+ uint32_t rsvd11[62];
+
+ /* 0xd00 ~ 0xdff */
+ uint32_t cstn_bmap[16]; /* CSTN bitmap write port */
+ uint32_t rsvd12[48];
+};
+
+/* LCD Function Enable Register */
+#define FER_EN (1 << 0) /* chip enabled */
+#define FER_ON (1 << 1) /* screen on */
+#define FER_YUV420 (3 << 2)
+#define FER_YUV422 (2 << 2)
+#define FER_YUV (1 << 3) /* 1:YUV, 0:RGB */
+
+/* LCD Panel Pixel Register */
+#define PPR_BPP_1 (0 << 0)
+#define PPR_BPP_2 (1 << 0)
+#define PPR_BPP_4 (2 << 0)
+#define PPR_BPP_8 (3 << 0)
+#define PPR_BPP_16 (4 << 0)
+#define PPR_BPP_24 (5 << 0)
+#define PPR_BPP_MASK (7 << 0)
+#define PPR_PWROFF (1 << 3)
+#define PPR_BGR (1 << 4)
+#define PPR_ENDIAN_LBLP (0 << 5)
+#define PPR_ENDIAN_BBBP (1 << 5)
+#define PPR_ENDIAN_LBBP (2 << 5)
+#define PPR_ENDIAN_MASK (3 << 5)
+#define PPR_RGB1 (PPR_BPP_1)
+#define PPR_RGB2 (PPR_BPP_2)
+#define PPR_RGB4 (PPR_BPP_4)
+#define PPR_RGB8 (PPR_BPP_8)
+#define PPR_RGB12 (PPR_BPP_16 | (2 << 7))
+#define PPR_RGB16_555 (PPR_BPP_16 | (1 << 7))
+#define PPR_RGB16_565 (PPR_BPP_16 | (0 << 7))
+#define PPR_RGB24 (PPR_BPP_24)
+#define PPR_RGB32 (PPR_BPP_24)
+#define PPR_RGB_MASK (PPR_BPP_MASK | (3 << 7))
+#define PPR_VCOMP_VSYNC (0 << 9)
+#define PPR_VCOMP_VBP (1 << 9)
+#define PPR_VCOMP_VAIMG (2 << 9)
+#define PPR_VCOMP_VFP (3 << 9)
+#define PPR_VCOMP_MASK (3 << 9)
+#define PPR_PANEL_6BIT (0 << 11)
+#define PPR_PANEL_8BIT (1 << 11)
+#define PPR_DITHER565 (0 << 12)
+#define PPR_DITHER555 (1 << 12)
+#define PPR_DITHER444 (2 << 12)
+#define PPR_HCLK_RESET (1 << 14)
+#define PPR_LCCLK_RESET (1 << 15)
+
+/* LCD Interrupt Enable Register */
+#define IER_FIFOUR (1 << 0)
+#define IER_NEXTFB (1 << 1)
+#define IER_VCOMP (1 << 2)
+#define IER_BUSERR (1 << 3)
+
+/* LCD Interrupt Status Register */
+#define ISR_FIFOUR (1 << 0)
+#define ISR_NEXTFB (1 << 1)
+#define ISR_VCOMP (1 << 2)
+#define ISR_BUSERR (1 << 3)
+
+/* LCD Horizontal Timing Control Register */
+#define HTCR_HBP(x) ((((x) - 1) & 0xff) << 24)
+#define HTCR_HFP(x) ((((x) - 1) & 0xff) << 16)
+#define HTCR_HSYNC(x) ((((x) - 1) & 0xff) << 8)
+#define HTCR_PL(x) (((x >> 4) - 1) & 0xff)
+
+/* LCD Vertical Timing Control Register 0 */
+#define VTCR0_VFP(x) (((x) & 0xff) << 24)
+#define VTCR0_VSYNC(x) ((((x) - 1) & 0x3f) << 16)
+#define VTCR0_LF(x) (((x) - 1) & 0xfff)
+
+/* LCD Vertical Timing Control Register 1 */
+#define VTCR1_VBP(x) ((x) & 0xff)
+
+/* LCD Polarity Control Register */
+#define PCR_IVS (1 << 0)
+#define PCR_IHS (1 << 1)
+#define PCR_ICK (1 << 2)
+#define PCR_IDE (1 << 3)
+#define PCR_IPWR (1 << 4)
+#define PCR_DIV(x) ((((x) - 1) & 0x7f) << 8)
+
+/* LCD Serial Panel Pixel Register */
+#define SPPR_SERIAL (1 << 0)
+#define SPPR_DELTA (1 << 1)
+#define SPPR_CS(x) ((x) << 2)
+#define SPPR_CS_RGB (0 << 2)
+#define SPPR_CS_BRG (1 << 2)
+#define SPPR_CS_GBR (2 << 2)
+#define SPPR_LSR (1 << 4)
+#define SPPR_AUO052 (1 << 5)
+
+/* LCD CCIR656 Register */
+#define CCIR_PAL (0 << 0)
+#define CCIR_NTSC (1 << 0)
+#define CCIR_P640 (0 << 1)
+#define CCIR_P720 (1 << 1)
+#define CCIR_PHASE(x) ((x) << 2)
+
+#endif /* __FTLCDC200_H */
diff --git a/include/lcd.h b/include/lcd.h
index 30225ed..14fa4fd 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -253,6 +253,39 @@ typedef struct vidinfo {
void init_panel_info(vidinfo_t *vid);
+#elif defined(CONFIG_FTLCDC200)
+
+typedef struct vidinfo {
+ ushort vl_col; /* Number of columns (i.e. 800) */
+ ushort vl_row; /* Number of rows (i.e. 600) */
+
+ u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2 ... 4 = 16 */
+
+ /* Timing Parameters */
+ u_char vl_fps; /* Frame per second */
+
+ u_char vl_hsw;
+ u_char vl_hbp;
+ u_char vl_hfp;
+
+ u_char vl_vsw;
+ u_char vl_vbp;
+ u_char vl_vfp;
+
+ /* Pre-defined FTLCDC200 register values */
+ u_long vl_enable; /* LCDEnable */
+ u_long vl_pixel; /* PanelPixel */
+ u_long vl_polarity;/* Polarity */
+ u_long vl_serial; /* SerialPanelPixel */
+ u_long vl_ccir656; /* CCIR656 */
+
+ /* Panel name */
+ char *vl_name;
+
+ ushort *cmap; /* Pointer to the colormap */
+ void *priv; /* Pointer to driver-specific data */
+} vidinfo_t;
+
#else
typedef struct vidinfo {
--
1.7.9.5
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