[U-Boot] USB host on MPC8349 not working
Mehresh Ramneek-B31383
B31383 at freescale.com
Thu Jul 18 19:23:21 CEST 2013
Hi Stewart,
Did you probe PHY CLK on external phy pin ? Is phy clock coming to the soc ?
Regards,
Ramneek
-----Original Message-----
From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Stewart Hamilton
Sent: Monday, July 08, 2013 12:08 PM
To: 'u-boot at lists.denx.de'
Subject: [U-Boot] USB host on MPC8349 not working
Hi
We have been using U- boot on our MPC8349 based board This was based on the v2009.06-rc2 circa May 2009 version.
This was configured to boot embedded linux from a Usb storage device.
Recently Micron release a revised version of this device (MTFDCAE002S ) and our current U-Boot is unable to load from it.
Booting into the Linux via other means has enabled us to program and verify this device works correctly in our system.
So it appears the 4 year old version of U-boot we are using is problem.
I have download the latest version of U-Boot and after numberer of changes to our configuration file got it to compile and boot
Unfortunately I cannot get it to configure the MPC8349 USB host controller.
We are running this USB controller in MPH mode.
After U-boot has booted into the console mode.
Typing USB start produced the following error..
(Re)start USB...
USB0: SET PHY CLOCK E0022500
USB PHY clock invalid!
lowlevel init failed
USB error: all controllers failed lowlevel init
Tracing this error shows it originates from the usb_phy_clk_valid routine in ehci-fsl.c I cannot find out why the ehci control port is unable to have the clock enabled.
I would appreciate any help or advice that people on here are able to give
Below are our Configuration head files and the low level board driver.
MPX8349.h
/*
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_MPC834x 1 /* MPC834x family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
// #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
#define CONFIG_SYS_TEXT_BASE 0xFC000000
#define CONFIG_PCI
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
#ifdef CONFIG_SYS_USB_HOST
/*
* Support USB
*/
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_EHCI_MPC83XX
#define CONFIG_DOS_PARTITION
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/* Current USB implementation supports the only USB controller,
* so we have to choose between the MPH or the DR ones */ #if 1 #define CONFIG_HAS_FSL_MPH_USB #else #define CONFIG_HAS_FSL_DR_USB #endif
#endif
#define CONFIG_PCI_33M
#ifdef CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#else
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
#endif
#ifdef CONFIG_PCISLAVE
#define CONFIG_PCI
#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
#endif /* CONFIG_PCISLAVE */
#ifndef CONFIG_SYS_CLK_FREQ
#ifdef CONFIG_PCI_66M
#define CONFIG_SYS_CLK_FREQ 66000000
#else
#define CONFIG_SYS_CLK_FREQ 59400000
#endif
#endif
#undef CONFIG_BOARD_EARLY_INIT_F /* don't call board_pre_init */
#undef CONFIG_BOARD_EARLY_INIT_R /* no board specific init */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
/*
* DDR Setup
*/
#undef CONFIG_DDR_ECC /* support DDR ECC function */
#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
* define CONFIG_FSL_DDR2 to use unified DDR driver
* undefine it to use old spd_sdram.c
*/
#undef CONFIG_FSL_DDR2
#ifdef CONFIG_FSL_DDR2
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x52
#define SPD_EEPROM_ADDRESS2 0x51
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#endif
/*
* 32-bit data path mode.
*
* Please note that using this mode for devices with the real density of 64-bit
* effectively reduces the amount of available memory due to the effect of
* wrapping around while translating address to row/columns, for example in the
* 256MB module the upper 128MB get aliased with contents of the lower
* 128MB); normally this define should be used for devices with real 32-bit
* data path.
*/
#undef CONFIG_DDR_32BIT
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING
/*
* DDRCDR - DDR Control Driver Register
*/
#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
*/
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#else
/*
* Manually set up DDR parameters
*/
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#if defined(CONFIG_DDR_II)
#error No such thing
#else
#define CONFIG_SYS_DDR_CONFIG (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN \
| SDRAM_CFG_2T_EN | SDRAM_CFG_SDRAM_TYPE_DDR1)
#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) \
| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| (4 << TIMING_CFG1_ACTTORW_SHIFT) \
| (TIMING_CFG1_CASLAT & TIMING_CASLAT) \
| (4 << TIMING_CFG1_REFREC_SHIFT) \
| (3 << TIMING_CFG1_WRREC_SHIFT) \
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (1 << TIMING_CFG1_WRTORD_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2 (TIMING_CFG2_CPO_DEF | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT))
/* #define CONFIG_SYS_DDR_CONTROL 0xc2000000 *//* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_INTERVAL ((0x0402 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT))
#if defined(CONFIG_DDR_32BIT)
#error TODO
#define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
#else
/* the default burst length is 4 - for 64-bit data path */
#define CONFIG_SYS_DDR_MODE (((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) << SDRAM_MODE_ESD_SHIFT) \
| ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) << SDRAM_MODE_SD_SHIFT) \
| ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) & MODE_CASLAT)) #endif #endif #endif
/*
* SDRAM on the Local Bus
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 16 /* max flash size in MB */
#undef CONFIG_SYS_FLASH_PROTECTION
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX_SET \
| OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
/* window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_RAMBOOT #else #undef CONFIG_SYS_RAMBOOT #endif
/*
* Local Bus LCRR and LBCR regs
* LCRR: DLL bypass, Clock divider is 4
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
* ??? on local bus
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM*/
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* SRAM on the Local Bus
*/
#define CONFIG_SYS_LBC_SRAM_BASE 0xF0000000 /* Localbus SRAM */
#define CONFIG_SYS_LBC_SRAM_SIZE 0x100000 /* max. LBC SRAM is 1 MB */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_LBC_SRAM_BASE \
| BR_PS_16 \
| BR_MS_UPMA \
| BR_V)
#define CONFIG_SYS_OR1_PRELIM ( OR_AM_1MB | OR_UPM_BI )
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_LBC_SRAM_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000019 /*64M*/
/*
* DiskOnChip on the Local Bus
*/
#define CONFIG_SYS_DOC_BASE 0xF1000000 /* Localbus DOC */
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_DOC_BASE | 0x1081)
#define CONFIG_SYS_OR2_PRELIM 0xfff00100
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_DOC_BASE
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /*64M*/
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
/*
* Optiscan FPGA on the Local Bus
*/
/*0xD0000000 used to give bigger address space for the FPGA (needed for burst accesss 128MB) */
#define CONFIG_SYS_LBC_OPTISCAN_FPGA_BASE 0xD0000000 /* Localbus base address for Optiscan FPGA */
#define CONFIG_SYS_LBC_OPTISCAN_FPGA_SIZE 0x08000000 /*128MB size */
/* 32 bit device at 0xD0000000 via UPMC */
#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_LBC_OPTISCAN_FPGA_BASE & BR_BA) \
| BR_PS_32 \
| BR_MS_UPMC \
| BR_V)
/* Burst access allowed, No relaxed timing, No external address bus delay */
#define CONFIG_SYS_OR3_PRELIM (OR_AM_128MB)
//Without these the LB mapping will not take effect
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_LBC_OPTISCAN_FPGA_BASE
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
#define CONFIG_SYS_LBC_BANK0_ADDRESS (CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_LBC_BANK1_ADDRESS (CONFIG_SYS_LBC_SRAM_BASE)
#define CONFIG_SYS_LBC_BANK2_ADDRESS (0)
#define CONFIG_SYS_LBC_BANK3_ADDRESS (CONFIG_SYS_LBC_OPTISCAN_FPGA_BASE)
/*
* UPM debug options. Depending on the bit pattern debug messages will be printed */
#define UPM_CRASH_DEBUG (0x80000000)
#define UPM_REGISTER_DETAILS (0x00000004)
#define UPM_ENGINE_TABLES (0x00000002)
#define UPM_STD_DETAILS (0x00000001)
#define UPM_DEBUG( dbgLevel, string, args...)\
if (dbgLevel & UPM_DEBUG_MESSAGES) \
{\
printf( string, ##args );\
}\
else\
{\
}
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
/* SPI */
#define CONFIG_MPC8XXX_SPI
#undef CONFIG_SOFT_SPI /* SPI bit-banged */
/* GPIOs. Used as SPI chip selects */
#undef CONFIG_SYS_GPIO1_PRELIM
#undef CONFIG_SYS_GPIO1_DIR // 0xC0000000 /* SPI CS on 0, LED on 1 */
#undef CONFIG_SYS_GPIO1_DAT // 0xC0000000 /* Both are active LOW */
/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
/* USB */
// #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
/* USB */
#define CONFIG_USB_POWER_MASK 0x00000002
#define CONFIG_EHCI_IS_TDI
/*
* General PCI
* Addresses are mapped 1-1.
*
*/
#define PCI_64BIT
#define CONFIG_SYS_PCI1_MEM_BASE 0xA0000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE 0xB0000000 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xD8000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 1M */
#if defined(CONFIG_PCI)
#define PCI_ONE_PCI1
#if defined(PCI_64BIT)
#undef PCI_ALL_PCI1
#undef PCI_TWO_PCI1
#undef PCI_ONE_PCI1
#endif
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_83XX_PCI_STREAMING /* XXX todo workout effect */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
#define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
/*
* TSEC configuration
*/
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management XXX is this GMII */
#define CONFIG_GMII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
// #define CONFIG_TSEC2 0
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */
/*
* Configure on-board EEPROM 24C256
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
/*
* Configure on-board RTC
*/
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_USB
#define CONFIG_CMD_EXT2
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* Cache Configuration
*/
#define CONFIG_SYS_DCACHE_SIZE 32768
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#if CONFIG_SYS_CLK_FREQ == 66000000
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_10X1 |\
HRCWL_VCO_1X4 |\
HRCWL_CORE_TO_CSB_2X1)
#elif CONFIG_SYS_CLK_FREQ == 59400000
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_9X1 |\
HRCWL_VCO_1X4 |\
HRCWL_CORE_TO_CSB_2X1)
#elif CONFIG_SYS_CLK_FREQ == 52800000
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_8X1 |\
HRCWL_VCO_1X4 |\
HRCWL_CORE_TO_CSB_2X1)
#elif CONFIG_SYS_CLK_FREQ == 33000000
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_8X1 |\
HRCWL_VCO_1X4 |\
HRCWL_CORE_TO_CSB_1_5X1)
#else
#error TODO #define CONFIG_SYS_HRCW_LOW
#endif
#ifdef CONFIG_PCISLAVE
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_AGENT |\
HRCWH_64_BIT_PCI |\
HRCWH_PCI1_ARBITER_DISABLE |\
HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII)
#else
#if defined(PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_64_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII)
#endif /* PCI_64BIT */
#endif /* CONFIG_PCISLAVE */
/*
* System performance
*/
//#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
//#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
//#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
// #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
#define CONFIG_SYS_SCCR_ENCCM 3 /* ENC clock mode (0-3) */
#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
#define CONFIG_SYS_SCCR_USBDRCM 3 /* USB DR controller's clock */
/* System IO Config */
#define CONFIG_SYS_SICRH SICRH_TSOBI1
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR - 256MB (0x0000_0000 - 0x0FFF_FFFF) */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
/* stack in DCACHE @ 128K (no backing mem) */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L (0)
#define CONFIG_SYS_IBAT3U (0)
#define CONFIG_SYS_IBAT4L (0)
#define CONFIG_SYS_IBAT4U (0)
#endif
/* Optiscan FPGA - 128MB (0xD000_0000 - 0xD7FF_FFFF)
PCI IO space - 16MB (0xD800_0000 - 0xD8FF_FFFF)
**** WARNING: CPU will reboot upon accessing these areas if these were not setup correctly **** */ #if defined(CONFIG_PCI)
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LBC_OPTISCAN_FPGA_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LBC_OPTISCAN_FPGA_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT5L (0)
#define CONFIG_SYS_IBAT5U (0)
#endif
/* IMMRBAR (MPC8349 HW Registers) - 1MB (0xE000_0000 - 0xE00F_FFFF */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
/* SRAM - 1MB (0xF000_0000 - 0xF00F_FFFF)
DOC Flash - 128MB (0xF100_0000 - 0xF8FF_FFFF)
Local bus Flash (Pri) - 16MB (0xFC00_0000 - 0xFCFF_FFFF) */
#define CONFIG_SYS_IBAT7L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
/* Ethernet configuration */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 3A:97:20:00:00:00
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 3A:97:20:80:00:00
#endif
/* IP configuration */
#define CONFIG_IPADDR 192.168.111.200
#define CONFIG_HOSTNAME EPM8349
#define CONFIG_GATEWAYIP 203.26.112.64
#define CONFIG_NETMASK 255.255.255.0
/* TFTP configuration */
#define CONFIG_SERVERIP 203.26.112.51
#define CONFIG_ROOTPATH "/srv/tftpboot/"
#define CONFIG_BOOTFILE "uImage"
/* Serial configuration */
#define CONFIG_BAUDRATE 115200
#endif /* __CONFIG_H */
MPX8349.C
/*
*
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#include <command.h>
#include <asm/mmu.h>
#include <pci.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
#include <libfdt.h>
#endif
#define IOSYNC asm("eieio")
#define ISYNC asm("isync")
#define SYNC asm("sync")
#define DDR_MAX_SIZE_PER_CS 0x20000000
#define UPM_DEBUG_MESSAGES 0
/* (UPM_CRASH_DEBUG | UPM_REGISTER_DETAILS | UPM_ENGINE_TABLES | UPM_STD_DETAILS) */
#if defined(DDR_CASLAT_20)
#define TIMING_CASLAT TIMING_CFG1_CASLAT_20
#define MODE_CASLAT DDR_MODE_CASLAT_20
#else
#define TIMING_CASLAT TIMING_CFG1_CASLAT_25
#define MODE_CASLAT DDR_MODE_CASLAT_25
#endif
#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10)
#define MEMORY_BANK0 0
#define MEMORY_BANK1 1
#define MEMORY_BANK2 2
#define MEMORY_BANK3 3
/* External definitions */
extern long spd_sdram (void);
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) void ddr_enable_ecc(unsigned int dram_size); #endif
/* Local functions */
static long int get_ddr_bank_size(short cs, volatile long *base); static void set_cs_bounds(short cs, long base, long size); static void set_cs_config(short cs, long config); static void set_ddr_config(void); void sram_init (void); void optiscan_fpga_init (void);
/* Local variable */
static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
/**************************************************************************
* DRAM initalization and size detection
*/
phys_size_t initdram (int board_type)
{
long bank_size;
long size;
int cs;
/* during size detection, set up the max DDRLAW size */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;
im->sysconf.ddrlaw[0].ar = (LBLAWAR_EN | LBLAWAR_2GB);
/* set CS bounds to maximum size */
for(cs = 0; cs < 4; ++cs) {
set_cs_bounds(cs,
CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
DDR_MAX_SIZE_PER_CS);
set_cs_config(cs, INITIAL_CS_CONFIG);
}
/* configure ddr controller */
set_ddr_config();
udelay(200);
/* enable DDR controller */
im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONFIG;
SYNC;
/* size detection */
debug("\n");
size = 0;
for(cs = 0; cs < 4; ++cs) {
debug("\nDetecting Bank%d\n", cs);
bank_size = get_ddr_bank_size(cs,
(volatile long*)(CONFIG_SYS_DDR_BASE + size));
size += bank_size;
debug("DDR Bank%d size: %u MiB\n\n", cs, (uint)(bank_size >> 20));
/* exit if less than one bank */
if(size < DDR_MAX_SIZE_PER_CS) break;
}
return size;
}
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
/**************************************************************************
* checkboard()
*/
int checkboard (void)
{
puts("Board: MPX8349-" BOARD_NAME "\n");
#ifdef CONFIG_PCI
volatile immap_t * immr;
u32 w, f;
immr = (immap_t *)CONFIG_SYS_IMMR;
if (!(immr->reset.rcwh & CONFIG_SYS_RCWH_PCIHOST)) {
printf("PCI: NOT in host mode..?!\n");
return 0;
}
/* get bus width */
w = 32;
if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
w = 64;
/* get clock */
f = CONFIG_83XX_CLKIN;
printf("PCI1: %d bit, %d MHz in Host mode\n", w, f / 1000000); #else
printf("PCI: disabled\n");
#endif
return 0;
}
/**************************************************************************
*
* Local functions
*
*************************************************************************/
/*************************************************************************
* Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
*/
static long int get_ddr_bank_size(short cs, volatile long *base) {
/* This array lists all valid DDR SDRAM configurations, with
* Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
* The last entry has to to have size equal 0 and is igonred during
* autodection. Bank sizes must be in increasing order of size
*/
struct {
long row;
long col;
long size;
} conf[] = {
{CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
{CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
{CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
{CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
{CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
{CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
{CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
{CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
{0, 0, 0}
};
int i;
int detected;
long size;
detected = -1;
for(i = 0; conf[i].size != 0; ++i) {
/* set sdram bank configuration */
set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
debug("Getting RAM size...\n");
size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
if((size == conf[i].size) && (i == detected + 1))
detected = i;
debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
conf[i].row,
conf[i].col,
conf[i].size >> 20,
base,
size >> 20);
}
if(detected == -1){
/* disable empty cs */
debug("\nNo valid configurations for CS%d, disabling...\n", cs);
set_cs_config(cs, 0);
return 0;
}
debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
/* configure cs ro detected params */
set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
conf[detected].col);
set_cs_bounds(cs, (long)base, conf[detected].size);
return(conf[detected].size);
}
/**************************************************************************
* Sets DDR bank CS bounds.
*/
static void set_cs_bounds(short cs, long base, long size) {
debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);
if(size == 0){
im->ddr.csbnds[cs].csbnds = 0x00000000;
} else {
im->ddr.csbnds[cs].csbnds =
((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((base + size - 1) >> CSBNDS_EA_SHIFT) &
CSBNDS_EA);
}
SYNC;
}
/**************************************************************************
* Sets DDR banks CS configuration.
* config == 0x00000000 disables the CS.
*/
static void set_cs_config(short cs, long config) {
debug("Setting config %08lx for cs %d\n", config, cs);
im->ddr.cs_config[cs] = config;
SYNC;
}
/**************************************************************************
* Sets DDR clocks, timings and configuration.
*/
static void set_ddr_config(void) {
/* clock control */
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
SYNC;
/* timing configuration */
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
SYNC;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
SYNC;
/* don't enable DDR controller yet */
im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONFIG & ~SDRAM_CFG_MEM_EN;
SYNC;
/* Set SDRAM mode */
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
SYNC;
/* Set fast SDRAM refresh rate */
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
SYNC;
/* Workaround for DDR6 Erratum
* see MPC8349E Device Errata Rev.8, 2/2006
* This workaround influences the MPC internal "input enables"
* dependent on CAS latency and MPC revision. According to errata
* sheet the internal reserved registers for this workaround are
* not available from revision 2.0 and up.
*/
/* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
* (0x200)
*/
if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
/* There is a internal reserved register at IMMRBAR+0x2F00
* which has to be written with a certain value defined by
* errata sheet.
*/
u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
#if defined(DDR_CASLAT_20)
*reserved_p = 0x201c0000;
#else
*reserved_p = 0x202c0000;
#endif
}
}
int misc_init_f (void)
{
sram_init();
optiscan_fpga_init();
return (0);
}
#if defined(CONFIG_SYS_BR3_PRELIM) && \
defined(CONFIG_SYS_OR3_PRELIM) && \
defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && \
defined(CONFIG_SYS_LBLAWAR3_PRELIM)
//IMPORTANT: Please update the following UPM version value when the UPMC table is updated.
#define UPMC_TABLE_VERSION ("EFB P2V2-3 : 2008-02-13")
uint upmc_table[] =
{
0x0ffffc00, 0x0ffffc40, 0x0ffcfc44, 0xfffffc01, //Words 0 to 3
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 4 to 7
0x0ffffc80, 0x0ffffc00, 0x0ffcfc8c, 0xfffffc41, //Words 8 to 11
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 12 to 15
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 16 to 19
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23
0x0ffbfc00, 0x0ff7fc44, 0xfffffc01, 0xfffffc00, //Words 24 to 27
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 28 to 31
0x0ffbfc80, 0x0ff7fc8c, 0xfffffc01, 0xfffffc00, //Words 32 to 35
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 36 to 39
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47
0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 48 to 51
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59
0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01 //Words 60 to 63 };
#endif
/*
* if MPX8349 is soldered with SRAM
*/
#if defined(CONFIG_SYS_BR1_PRELIM) \
&& defined(CONFIG_SYS_OR1_PRELIM) \
&& defined(CONFIG_SYS_LBLAWBAR1_PRELIM) \
&& defined(CONFIG_SYS_LBLAWAR1_PRELIM)
/*
* Initialize SRAM memory on the Local Bus.
*/
uint upma_table[] =
{
0xcc0ffc00, 0x000ffc00, 0x000cfd00, 0x000cfc04,
0x770dfc01, 0xfffffc01, 0xfffffc00, 0xfffffc01,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xcc0ffc00, 0x0003fd00, 0x0003fc00, 0x000ffc05,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xfffffc03, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
0xfffffc03, 0xff3ffc00, 0xfffffc00, 0xfffffc01 };
void sram_init (void)
{
puts("SRAM: ");
im->im_lbc.mcmr = MxMR_G0CLx_A10 | MxMR_RLFx_8X | MxMR_WLFx_8X | MxMR_TLFx_1X;
upmconfig(UPMA, upma_table, sizeof(upma_table)/sizeof(upma_table[0]));
puts("Configured\n");
}
#else
void
sram_init(void)
{
puts("SRAM on Local Bus is NOT available!\n"); } #endif
#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) {
doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && \
defined(CONFIG_SYS_OR3_PRELIM) && \
defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && \
defined(CONFIG_SYS_LBLAWAR3_PRELIM)
void optiscan_fpga_init (void)
{
printf("UPM-C Ram array (Optiscan version %s): ", UPMC_TABLE_VERSION );
im->im_lbc.mcmr = MxMR_G0CLx_A10 | MxMR_RLFx_8X | MxMR_WLFx_8X | MxMR_TLFx_1X;
upmconfig(UPMC, upmc_table, sizeof(upmc_table)/sizeof(upmc_table[0]));
UPM_DEBUG( UPM_STD_DETAILS, "\nOptiscan FPGA: Mapped\n"); } #endif
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd) {
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif
Stewart
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