[U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific

[Thierry Reding]

From: Thierry Reding <treding at nvidia.com>

Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.

Signed-off-by: Thierry Reding <treding at nvidia.com>
---
 include/configs/tegra-common.h    | 2 --
 include/configs/tegra114-common.h | 3 +++
 include/configs/tegra20-common.h  | 3 +++
 include/configs/tegra30-common.h  | 3 +++
 4 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index cb9e7c3..056207b 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -33,8 +33,6 @@
 #define CONFIG_TEGRA			/* which is a Tegra generic machine */
 #define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #include <asm/arch/tegra.h>		/* get chip and board defs */
 
 /*
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 44e98e5..c3de9a9 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -18,6 +18,9 @@
 #define _TEGRA114_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * NS16550 Configuration
  */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index d5abecb..b334b33 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -25,6 +25,9 @@
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 7ea36be..a72dc13 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -25,6 +25,9 @@
 #define _TEGRA30_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */
-- 
1.8.1.5