[U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

[Fabio Estevam]

On Wed, Jul 17, 2013 at 4:46 PM, Troy Kisky
<troy.kisky at boundarydevices.com> wrote:
> The old value of 0x000e0030 will cause ethernet
> timeout issues on the sabrelite and possibly other
> boards using the KSZ9021.
> I have no explanation as to why.
>
> But this is a correct change, the TRM will be updated
> to show that 00b is the only valid setting for bits
> 19-18 of DRAM_RESET.
>
> My thanks go to Liu Hui(Jason) for this information.
>
> Signed-off-by: Troy Kisky <troy.kisky at boundarydevices.com>

Acked-by: Fabio Estevam <fabio.estevam at freescale.com>