[U-Boot] [PATCH 1/1] ddr cfg: DRAM_RESET needs 0x00020030

[Dirk Behme]

On 17.07.2013 21:46, Troy Kisky wrote:
> The old value of 0x000e0030 will cause ethernet
> timeout issues on the sabrelite and possibly other
> boards using the KSZ9021.
> I have no explanation as to why.
>
> But this is a correct change, the TRM will be updated
> to show that 00b is the only valid setting for bits
> 19-18 of DRAM_RESET.
>
> My thanks go to Liu Hui(Jason) for this information.
>
> Signed-off-by: Troy Kisky <troy.kisky at boundarydevices.com>

Acked-by: Dirk Behme <dirk.behme at de.bosch.com>

Thanks

Dirk

> ---
>   board/boundary/nitrogen6x/ddr-setup.cfg | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg
> index c315812..e5f8add 100644
> --- a/board/boundary/nitrogen6x/ddr-setup.cfg
> +++ b/board/boundary/nitrogen6x/ddr-setup.cfg
> @@ -74,7 +74,7 @@ DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
>   DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
>   DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
>
> -DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
> +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
>   DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
>   DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000