[U-Boot] [PATCH] powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]
York Sun
yorksun at freescale.com
Mon Jul 22 18:35:26 CEST 2013
From: James Yang <James.Yang at freescale.com>
The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but
the mask omitted the LSB. This patch provides a 2-bit wide mask.
Signed-off-by: James Yang <James.Yang at freescale.com>
Signed-off-by: York Sun <yorksun at freescale.com>
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 26c42f7..b817935 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -367,7 +367,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
ddr->timing_cfg_3 = (0
| ((ext_pretoact & 0x1) << 28)
- | ((ext_acttopre & 0x2) << 24)
+ | ((ext_acttopre & 0x3) << 24)
| ((ext_acttorw & 0x1) << 22)
| ((ext_refrec & 0x1F) << 16)
| ((ext_caslat & 0x3) << 12)
--
1.7.9.5
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