[U-Boot] TFTP timeouts, i.mx fec problem?

[Ruud Commandeur]

In fact, it does wait for the link-up bit in miiphy_wait_aneg( ), which is called from fec_open. So after the init and before starting to send the first packet, you notice a delay for about half as second (enabled some debug printing) waiting for this bit to get set and then the phy should be up and running. I tried adding to wait for the the auto-neg complete bit as well, but this doesn't solve it. For some reason, the phy needs like 200 - 600 msecs extra in most cases before the 1st packet can be sent.

Some other remark: I get the idea of starting the kernel with a "virgin-like" phy and mac, which I will not argue about. But in fact the phy is reset and initialised befóre each transfer. After the transfer, the mac is halted, but the phy is not reset again. Also, I am pretty sure (sorry, I'm not at the office right now), that the phy is reset if the kernel starts. I know this because I did some tweaking to the evk dts, where the phy reset pulse can be configured:

		mac0: ethernet at 800f0000 {
			phy-mode = "rmii";
			pinctrl-names = "default";
			pinctrl-0 = <&mac0_pins_a>;
			phy-supply = <&reg_fec_3v3>;
			phy-reset-gpios = <&gpio4 13 0>;
			phy-reset-duration = <100>;
			status = "okay";
		};

Regards,

Ruud


-----Oorspronkelijk bericht-----
Van: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
Verzonden: vr 31-5-2013 21:09
Aan: Wolfgang Denk
CC: Stefano Babic; Ruud Commandeur; U-Boot list
Onderwerp: Re: [U-Boot] TFTP timeouts, i.mx fec problem?
 
On 5/31/2013 11:58 AM, Wolfgang Denk wrote:
> Dear Stefano Babic,
>
> In message <51A8C5DA.3090605 at denx.de> you wrote:
>>> The question is if there is no better way to wait for the PHY to
>>> become (really) ready?
>> The phy is reinitialized after each transaction - the safiest condition
>> to boot afterwards the kernel. Or we need a way to stop the phy only
> Yes, that is clear, we fully agree on that.
>
> But can we not test for "autoneogitation completed, link up and
> running" before we send the first packet?
>
> Or rather - why do we have this issue appearently only on i.MX?  We
> don't see this on other ARM or on PowerPC?
>
> Best regards,
>
> Wolfgang Denk
>
Think of this as incentive to convert to the board to  PHYLIB.

Troy