[U-Boot] [PATCH 1/1] Add support of IB8315 board
Sergey Gerasimov
Sergey.Gerasimov at astrosoft-development.com
Mon Jun 3 16:51:00 CEST 2013
Signed-off-by: Sergey Gerasimov <Sergey.Gerasimov at astrosoft-development.com>
---
board/ib8315/Makefile | 49 +++
board/ib8315/ib8315.c | 194 +++++++++++
board/ib8315/sdram.c | 123 +++++++
board/ib8315/tqm8315.c | 194 +++++++++++
boards.cfg | 1 +
drivers/block/fsl_sata.c | 21 ++
drivers/block/fsl_sata.h | 7 +
include/configs/IB8315.h | 839 +++++++++++++++++++++++++++++++++++++++++++++++
include/sata.h | 4 +
9 files changed, 1432 insertions(+)
create mode 100644 board/ib8315/Makefile
create mode 100644 board/ib8315/ib8315.c
create mode 100644 board/ib8315/sdram.c
create mode 100644 board/ib8315/tqm8315.c
create mode 100644 include/configs/IB8315.h
diff --git a/board/ib8315/Makefile b/board/ib8315/Makefile
new file mode 100644
index 0000000..aa74213
--- /dev/null
+++ b/board/ib8315/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+
+COBJS := tqm8315.o sdram.o
+
+COBJS-$(CONFIG_PCIE) += pcie.o
+
+COBJS-$(CONFIG_PCI) += pci.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ib8315/ib8315.c b/board/ib8315/ib8315.c
new file mode 100644
index 0000000..b21940d
--- /dev/null
+++ b/board/ib8315/ib8315.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (C) 2009 TQ-Systems GmbH
+ *
+ * Author: Thomas Waehner <thomas.waehner at tqs.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <sata.h>
+#include <asm/io.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_83XX_GENERIC_PCIE)
+#if !defined(CONFIG_FSL_SERDES)
+#error PCIe operation needs CONFIG_FSL_SERDES
+#endif
+#endif
+
+#define PHYCTRLCFG_REFCLK_MASK 0x00000070
+#define PHYCTRLCFG_REFCLK_125MHZ 0x00000070
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_FSL_SERDES
+ /* Setup SERDES for PCIe operation */
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+#endif /* CONFIG_FSL_SERDES */
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: TQM8315\n");
+ return 0;
+}
+
+static struct pci_region pci_regions[] = {
+ {
+ .bus_start = CONFIG_SYS_PCI_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCI_MEM_PHYS,
+ .size = CONFIG_SYS_PCI_MEM_SIZE,
+ .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ .bus_start = CONFIG_SYS_PCI_MMIO_BASE,
+ .phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
+ .size = CONFIG_SYS_PCI_MMIO_SIZE,
+ .flags = PCI_REGION_MEM
+ },
+ {
+ .bus_start = CONFIG_SYS_PCI_IO_BASE,
+ .phys_start = CONFIG_SYS_PCI_IO_PHYS,
+ .size = CONFIG_SYS_PCI_IO_SIZE,
+ .flags = PCI_REGION_IO
+ }
+};
+
+#ifdef CONFIG_83XX_GENERIC_PCIE
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+ {
+ .size = 0,
+ }
+};
+
+static struct pci_region pcie_regions_1[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE2_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+ .size = CONFIG_SYS_PCIE2_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+ {
+ .size = 0,
+ }
+};
+#endif
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci_regions };
+#ifdef CONFIG_83XX_GENERIC_PCIE
+ volatile sysconf83xx_t *sysconf = &immr->sysconf;
+ volatile law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+#endif
+
+ /* Enable all 3 PCI_CLK_OUTPUTs. */
+ clk->occr |= 0xe0000000;
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ mpc83xx_pci_init(1, reg);
+
+#ifdef CONFIG_83XX_GENERIC_PCIE
+ /* Configure the clock for PCIE controller */
+ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+ SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ out_be32(&sysconf->pecr2, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(2, pcie_reg);
+#endif
+}
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void)
+{
+#ifdef CONFIG_FSL_SATA
+ /* Init SATA PHY CLK rate which must only be done once at startup */
+ init_mpc8315_sata_phy();
+#endif
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Initialize TSECs first */
+ return pci_eth_init(bis);
+}
diff --git a/board/ib8315/sdram.c b/board/ib8315/sdram.c
new file mode 100644
index 0000000..734362a
--- /dev/null
+++ b/board/ib8315/sdram.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2009 TQ-Systems GmbH
+ *
+ * Author: Thomas Waehner <thomas.waehner at tqs.de>
+ *
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Authors: Nick.Spence at freescale.com
+ * Wilson.Lo at freescale.com
+ * scottwood at freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+ volatile u32 law;
+ int i;
+ /* configure local access window for SDRAM address range */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+ /*
+ * According to MPC8315ERM Rev. 1 read back last configured local
+ * access window configuration register, followed by an isync.
+ */
+ law = im->sysconf.ddrlaw[0].ar;
+ isync();
+
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+
+
+ /*
+ * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+ * or the DDR2 controller may fail to initialize correctly.
+ */
+ for (i = 0; i < 50; i++)
+ udelay(1000);
+
+ im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+ /* Currently we use only one CS, so disable the other bank. */
+ im->ddr.cs_config[1] = 0;
+
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+
+ if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
+ else
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_md_cntl = CONFIG_SYS_DDR_SDRAM_MD_CNTL;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ eieio();
+
+ /*
+ * According to Freescale's application note AN2583 Rev. 8 wait 200 us
+ * after the DLL is locked before enabling the DDR controller.
+ */
+ udelay(200);
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ eieio();
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ u32 msize;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM */
+ msize = fixed_sdram();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
diff --git a/board/ib8315/tqm8315.c b/board/ib8315/tqm8315.c
new file mode 100644
index 0000000..b21940d
--- /dev/null
+++ b/board/ib8315/tqm8315.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (C) 2009 TQ-Systems GmbH
+ *
+ * Author: Thomas Waehner <thomas.waehner at tqs.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <sata.h>
+#include <asm/io.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_83XX_GENERIC_PCIE)
+#if !defined(CONFIG_FSL_SERDES)
+#error PCIe operation needs CONFIG_FSL_SERDES
+#endif
+#endif
+
+#define PHYCTRLCFG_REFCLK_MASK 0x00000070
+#define PHYCTRLCFG_REFCLK_125MHZ 0x00000070
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_FSL_SERDES
+ /* Setup SERDES for PCIe operation */
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+#endif /* CONFIG_FSL_SERDES */
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: TQM8315\n");
+ return 0;
+}
+
+static struct pci_region pci_regions[] = {
+ {
+ .bus_start = CONFIG_SYS_PCI_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCI_MEM_PHYS,
+ .size = CONFIG_SYS_PCI_MEM_SIZE,
+ .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ .bus_start = CONFIG_SYS_PCI_MMIO_BASE,
+ .phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
+ .size = CONFIG_SYS_PCI_MMIO_SIZE,
+ .flags = PCI_REGION_MEM
+ },
+ {
+ .bus_start = CONFIG_SYS_PCI_IO_BASE,
+ .phys_start = CONFIG_SYS_PCI_IO_PHYS,
+ .size = CONFIG_SYS_PCI_IO_SIZE,
+ .flags = PCI_REGION_IO
+ }
+};
+
+#ifdef CONFIG_83XX_GENERIC_PCIE
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+ {
+ .size = 0,
+ }
+};
+
+static struct pci_region pcie_regions_1[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE2_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+ .size = CONFIG_SYS_PCIE2_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+ {
+ .size = 0,
+ }
+};
+#endif
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci_regions };
+#ifdef CONFIG_83XX_GENERIC_PCIE
+ volatile sysconf83xx_t *sysconf = &immr->sysconf;
+ volatile law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+#endif
+
+ /* Enable all 3 PCI_CLK_OUTPUTs. */
+ clk->occr |= 0xe0000000;
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ mpc83xx_pci_init(1, reg);
+
+#ifdef CONFIG_83XX_GENERIC_PCIE
+ /* Configure the clock for PCIE controller */
+ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+ SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ out_be32(&sysconf->pecr2, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(2, pcie_reg);
+#endif
+}
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void)
+{
+#ifdef CONFIG_FSL_SATA
+ /* Init SATA PHY CLK rate which must only be done once at startup */
+ init_mpc8315_sata_phy();
+#endif
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Initialize TSECs first */
+ return pci_eth_init(bis);
+}
diff --git a/boards.cfg b/boards.cfg
index e2a8d42..97ef108 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -734,6 +734,7 @@ MVBLM7 powerpc mpc83xx mvblm7 matrix_
SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP
TQM834x powerpc mpc83xx tqm834x tqc
+IB8315 powerpc mpc83xx ib8315 -
suvd3 powerpc mpc83xx km83xx keymile - suvd3:SUVD3
kmvect1 powerpc mpc83xx km83xx keymile - suvd3:KMVECT1
tuge1 powerpc mpc83xx km83xx keymile - tuxx1:TUGE1
diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c
index 1f9d7b0..dc834a0 100644
--- a/drivers/block/fsl_sata.c
+++ b/drivers/block/fsl_sata.c
@@ -87,6 +87,27 @@ static int ata_wait_register(unsigned __iomem *addr, u32 mask,
return (i < timeout_msec) ? 0 : -1;
}
+#if defined(CONFIG_MPC8315)
+#ifndef CONFIG_SYS_SATA_CLK
+#define CONFIG_SYS_SATA_CLK PHYCTRLCFG_REFCLK_75MHZ
+#endif
+/* If you have a MPC8315 board, you can call this function from last_stage_init
+ * call to setup the MPC8315 specific PHY clocking parameter */
+void init_mpc8315_sata_phy(void)
+{
+ u32 val32;
+ fsl_sata_reg_t *reg;
+
+ reg = (fsl_sata_reg_t *)(CONFIG_SYS_IMMR + 0x18000);
+
+ /* Configure PHY */
+ val32 = in_le32(®->phyctrlcfg);
+ val32 &= ~PHYCTRLCFG_REFCLK_MASK;
+ val32 |= CONFIG_SYS_SATA_CLK;
+ out_le32(®->phyctrlcfg, val32);
+}
+#endif
+
int init_sata(int dev)
{
u32 length, align;
diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h
index a9c27bc..0572a48 100644
--- a/drivers/block/fsl_sata.h
+++ b/drivers/block/fsl_sata.h
@@ -172,6 +172,13 @@ typedef struct fsl_sata_reg {
#define PHYCTRLCFG_FPRFTI_MASK 0x00000018
#define PHYCTRLCFG_LOOPBACK_MASK 0x0000000e
+#define PHYCTRLCFG_REFCLK_MASK 0x00000070
+#define PHYCTRLCFG_REFCLK_50MHZ 0x00000050
+#define PHYCTRLCFG_REFCLK_75MHZ 0x00000000
+#define PHYCTRLCFG_REFCLK_100MHZ 0x00000060
+#define PHYCTRLCFG_REFCLK_125MHZ 0x00000070
+#define PHYCTRLCFG_REFCLK_150MHZ 0x00000020
+
/*
* Command Header Entry
*/
diff --git a/include/configs/IB8315.h b/include/configs/IB8315.h
new file mode 100644
index 0000000..dc897bd
--- /dev/null
+++ b/include/configs/IB8315.h
@@ -0,0 +1,839 @@
+/*
+ * Copyright (C) 2009 TQ-Systems GmbH
+ *
+ * Author: Thomas Waehner <thomas.waehner at tqs.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
+#define CONFIG_SYS_TEXT_BASE_SPL 0x81f00000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_NAND_U_BOOT */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x80000000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC831x 1 /* MPC831x CPU family */
+#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
+#define CONFIG_TQM8315 1 /* TQM8315 board specific */
+
+
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.666 MHz, then
+ * CSB = 133.333 MHz, CORE = 400 MHz, DDR-Contr. inp. = 266.666 MHz
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_SVCOD_DIV_2 |\
+ HRCWL_CSB_TO_CLKIN_2X1 |\
+ HRCWL_CORE_TO_CSB_3X1)
+#define CONFIG_SYS_HRCW_HIGH_BASE (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_TSEC1M_IN_RGMII |\
+ HRCWH_TSEC2M_IN_RGMII |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LALE_NORMAL)
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+ HRCWH_FROM_0XFFF00100 |\
+ HRCWH_ROM_LOC_NAND_SP_8BIT |\
+ HRCWH_RL_EXT_NAND)
+#else
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+ HRCWH_FROM_0X00000100 |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY)
+#endif
+
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH 0x00000000
+#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_LAST_STAGE_INIT /* call last_stage_init for SATA init */
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR 0xE0000000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency prio is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE 0x00080001
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE 256 /* MiB */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
+
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ODT_WR_ALL \
+ | CSCONFIG_BANK_BIT_3 \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
+ /* 0x80044102 */
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (1 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (1 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (1 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (5 << TIMING_CFG0_MRS_CYC_SHIFT))
+ /* 0x00110105 */
+#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (9 << TIMING_CFG1_REFREC_SHIFT) \
+ | (2 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
+ /* 0x26259222 */
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (3 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x119048c7 */
+#define CONFIG_SYS_DDR_INTERVAL ((520 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+ /* 0x02080100 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_32 \
+ | SDRAM_CFG_HSE)
+ /* 0x43080008 */
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_MODE ((0x440e << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0232 << SDRAM_MODE_SD_SHIFT))
+ /* 0x440e0232 */
+#define CONFIG_SYS_DDR_MODE2 0x8000C000
+#define CONFIG_SYS_DDR_SDRAM_MD_CNTL 0x00000000
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00200000
+
+/*
+ * The reserved memory
+ */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+ #define CONFIG_SYS_RAMBOOT
+#else
+ #undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KiB for Mon*/
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xF0000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR 0x00040000
+#define CONFIG_FSL_ELBC 1
+
+
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size in MiB */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection */
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size */
+
+#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+
+ /* 0x80001001 */
+/* Flash timing for LBC = 66.666 MHz */
+#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_SCY_3 \
+ | OR_GPCM_TRLX_SET)
+ /* 0xFC000834 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
+ (CONFIG_SYS_FLASH_BASE \
+ + ((CONFIG_SYS_FLASH_SIZE / 2) << 20))}
+#define CONFIG_SYS_MAX_FLASH_SECT 259
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ * define CONFIG_NAND to use it
+ */
+#undef CONFIG_NAND
+
+#ifdef CONFIG_NAND
+ #define CONFIG_SYS_NAND_BASE 0xE0600000
+ #define CONFIG_SYS_MAX_NAND_DEVICE 1
+ #define CONFIG_MTD_NAND_VERIFY_WRITE 1
+ #define CONFIG_NAND_FSL_ELBC 1
+
+ /*
+ * Use HW ECC
+ * Port Size = 8 bit
+ * MSEL = FCM
+ */
+ #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
+ | (2 << BR_DECC_SHIFT) \
+ | BR_PS_8 \
+ | BR_MS_FCM \
+ | BR_V)
+ #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* address mask 32 KiB */ \
+ | OR_FCM_PGS \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_RST)
+
+ #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
+ #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32 KiB */
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_FSL_I2C
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES {0x50} /* Don't probe config eeprom */
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_SYS_I2C_DTT_ADDR 0x48 /* Sensor base address */
+/* Use the following define if you only want the TQM8315 on-module sensor */
+#define CONFIG_DTT_SENSORS {0}
+/*
+ * Use the following define if it is on a STK85xxNG
+ * to read the temp sensors there, too
+ */
+/* #define CONFIG_DTT_SENSORS {0, 1, 2, 3} */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_PCI
+
+#ifdef CONFIG_PCI
+ #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
+ #define CONFIG_83XX_GENERIC_PCIE 1
+ #define CONFIG_PCIE
+#endif
+
+#ifdef CONFIG_83XX_GENERIC_PCI
+ #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
+ #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
+ #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MiB */
+ #define CONFIG_SYS_PCI_MMIO_BASE 0xD0000000
+ #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
+ #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256 MiB */
+ #define CONFIG_SYS_PCI_IO_BASE (CONFIG_SYS_IMMR + 0x03000000)
+ #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BASE
+ #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1 MiB */
+
+ #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
+ #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
+ #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
+
+ #define CONFIG_NET_MULTI
+ #define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+ #define CONFIG_EEPRO100 /* Intel Pro/100 NIC support */
+ #define CONFIG_E1000 /* Intel Pro/1000 NIC support */
+ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+ #ifndef CONFIG_NET_MULTI
+ #define CONFIG_NET_MULTI 1
+#endif
+
+#ifdef CONFIG_83XX_GENERIC_PCIE
+ #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
+
+ #define CONFIG_SYS_PCIE1_BASE 0x40000000
+ #define CONFIG_SYS_PCIE1_CFG_BASE 0x50000000
+ #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
+ #define CONFIG_SYS_PCIE1_MEM_BASE 0x40000000
+ #define CONFIG_SYS_PCIE1_MEM_PHYS 0x40000000
+ #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
+ #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+ #define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_IMMR + 0x03100000)
+ #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
+
+ #define CONFIG_SYS_PCIE2_BASE 0x60000000
+ #define CONFIG_SYS_PCIE2_CFG_BASE 0x70000000
+ #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
+ #define CONFIG_SYS_PCIE2_MEM_BASE 0x60000000
+ #define CONFIG_SYS_PCIE2_MEM_PHYS 0x60000000
+ #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
+ #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+ #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_IMMR + 0x03180000)
+ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
+ #endif
+#endif
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM 1
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ #define CONFIG_USB_EHCI
+ #define CONFIG_USB_EHCI_FSL
+ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+ #define CONFIG_DOS_PARTITION
+ #define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_GMII
+
+#define CONFIG_PHYLIB 1
+#define CONFIG_PHY_VITESSE 1
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define TSEC1_PHY_ADDR 2
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS (TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME "eTSEC0"
+
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1 0xe3000
+
+/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+/* Choose the phy setting for your SATA clock
+ * The following values are possible for CONFIG_SYS_SATA_CLK:
+ * PHYCTRLCFG_REFCLK_50MHZ
+ * PHYCTRLCFG_REFCLK_75MHZ
+ * PHYCTRLCFG_REFCLK_100MHZ
+ * PHYCTRLCFG_REFCLK_125MHZ
+ * PHYCTRLCFG_REFCLK_150MHZ
+ */
+#define CONFIG_SYS_SATA_CLK PHYCTRLCFG_REFCLK_125MHZ
+
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1_OFFSET 0x18000
+#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR \
+ + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2_OFFSET 0x19000
+#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR \
+ + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+ #define CONFIG_LBA48
+ #define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * MTD
+ */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+ #define CONFIG_ENV_IS_IN_FLASH 1
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128 KiB (one sector) per env */
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
+ + CONFIG_SYS_MONITOR_LEN) /* env1 */
+ #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR \
+ + CONFIG_ENV_SECT_SIZE) /* env2 */
+ #define CONFIG_ENV_SIZE 0x2000
+#else
+ #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
+ #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#ifdef CONFIG_MTD_PARTITIONS
+ #define CONFIG_CMD_MTDPARTS
+ #define MTDIDS_DEFAULT "nor0=80000000.flash"
+ #define MTDPARTS_DEFAULT "mtdparts=80000000.flash:" \
+ "512k(uboot)ro," \
+ "128k(env1)ro," \
+ "128k(env2)ro," \
+ "128k(dtb)," \
+ "2m(kernel)," \
+ "4m(root)," \
+ "-(user)"
+#endif
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+
+ #define CONFIG_CMD_DATE
+ #define CONFIG_CMD_DTT
+ #define CONFIG_CMD_EEPROM
+ #define CONFIG_CMD_I2C
+#endif
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ #define CONFIG_CMD_USB
+#endif
+
+#ifdef CONFIG_NAND
+ #define CONFIG_CMD_NAND
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
+#endif
+
+#ifdef CONFIG_FSL_SATA
+ #define CONFIG_CMD_SATA
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_FSL_SATA)
+ #define CONFIG_CMD_EXT2
+ #define CONFIG_CMD_FAT
+#endif
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MiB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2 HID2_HBE
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_IMMR \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_IMMR \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT1L (CONFIG_SYS_FLASH_BASE \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATL_PP_10)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
+ | BATU_BL_128K \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+
+/* DDR: 512MiB cache cacheable */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_SDRAM_BASE \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_SDRAM_BASE \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+
+#ifdef CONFIG_PCI
+ /* PCI MEM space: cacheable */
+ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MEM_PHYS \
+ | BATL_PP_10 \
+ | BATL_MEMCOHERENCE)
+ #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MEM_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+ #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
+ #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+
+ /* PCI MMIO space: cache-inhibit and guarded */
+ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MMIO_PHYS \
+ | BATL_PP_10 \
+ | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+ #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MMIO_PHYS \
+ | BATU_BL_256M \
+ | BATU_VS \
+ | BATU_VP)
+ #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
+ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+
+ #define CONFIG_SYS_IBAT7L 0
+ #define CONFIG_SYS_IBAT7U 0
+ #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+ #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+#else
+ #define CONFIG_SYS_IBAT5L 0
+ #define CONFIG_SYS_IBAT5U 0
+ #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
+ #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+ #define CONFIG_SYS_IBAT6L 0
+ #define CONFIG_SYS_IBAT6U 0
+ #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
+ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+ #define CONFIG_SYS_IBAT7L 0
+ #define CONFIG_SYS_IBAT7U 0
+ #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+ #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+ #define CONFIG_HAS_ETH0
+ #define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define MK_STR(x) #x
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ubootfile=u-boot_tqm8315.bin\0" \
+ "ubootaddr_f=" MK_STR(CONFIG_SYS_FLASH_BASE) "\0" \
+ "load=tftpboot $loadaddr $ubootfile\0" \
+ "update=protect off $ubootaddr_f +$filesize;" \
+ "erase $ubootaddr_f +$filesize;" \
+ "cp.b $loadaddr $ubootaddr_f $filesize\0" \
+ "upd=run load update\0" \
+ "fdtaddr_r=400000\0" \
+ "fdtaddr_f=800C0000\0" \
+ "fdtfile=tqm8315.dtb\0" \
+ "updfdt=tftp $loadaddr $fdtfile;" \
+ "protect off $fdtaddr_f +$filesize;" \
+ "erase $fdtaddr_f +$filesize;" \
+ "cp.b $loadaddr $fdtaddr_f $filesize\0" \
+ "kerneladdr_f=800E0000\0" \
+ "bootfile=uImage_tqm8315\0" \
+ "updkrn=tftp $loadaddr $bootfile;" \
+ "protect off $kerneladdr_f +$filesize;" \
+ "erase $kerneladdr_f +$filesize;" \
+ "cp.b $loadaddr $kerneladdr_f $filesize\0" \
+ "ramdiskaddr_r=1000000\0" \
+ "ramdiskaddr_f=802E0000\0" \
+ "ramdiskfile=uRamdisk\0" \
+ "updrd=tftp $loadaddr $ramdiskfile;" \
+ "protect off $ramdiskaddr_f +$filesize;" \
+ "erase $ramdiskaddr_f +$filesize;" \
+ "cp.b $loadaddr $ramdiskaddr_f $filesize\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "flashboot=" CONFIG_FLASHBOOTCOMMAND "\0" \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "usb_phy_type=utmi\0" \
+ "hostname=TQM8315\0" \
+ MTDPARTS_DEFAULT "\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:" \
+ "$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate " \
+ "mtdparts=$mtdparts " \
+ "$othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr_r $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr_r"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:" \
+ "$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate " \
+ "mtdparts=$mtdparts " \
+ "$othbootargs;" \
+ "tftp $ramdiskaddr_r $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr_r $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr_r $fdtaddr_r"
+
+#define CONFIG_FLASHBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:" \
+ "$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate " \
+ "mtdparts=$mtdparts " \
+ "$othbootargs;" \
+ "bootm $kerneladdr_f $ramdiskaddr_f $fdtaddr_f"
+
+#define CONFIG_BOOTCOMMAND "run flashboot"
+
+#endif /* __CONFIG_H */
diff --git a/include/sata.h b/include/sata.h
index c95dc56..c20e8dc 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -12,4 +12,8 @@ int __sata_initialize(void);
extern block_dev_desc_t sata_dev_desc[];
+#if defined(CONFIG_MPC8315)
+void init_mpc8315_sata_phy(void);
+#endif
+
#endif
--
1.7.11.7
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