[U-Boot] [PATCH 2/3] arm: omap3: spl: Fix problem with 8bit NAND devices
Stefan Roese
sr at denx.de
Fri Jun 14 10:55:00 CEST 2013
Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit
access. This patch adds support for 8bit NAND devices as well.
Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Tom Rini <trini at ti.com>
---
arch/arm/cpu/armv7/omap3/mem.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
index d04a5a1..378ba81 100644
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ b/arch/arm/cpu/armv7/omap3/mem.c
@@ -34,6 +34,17 @@
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
+#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+ SMNAND_GPMC_CONFIG1,
+ SMNAND_GPMC_CONFIG2,
+ SMNAND_GPMC_CONFIG3,
+ SMNAND_GPMC_CONFIG4,
+ SMNAND_GPMC_CONFIG5,
+ SMNAND_GPMC_CONFIG6,
+ 0,
+};
+#else
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
@@ -42,6 +53,7 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6, 0
};
+#endif
#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_CMD_ONENAND)
--
1.8.2.3
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