[U-Boot] [PATCH 1/2] powerpc/85xx: Add C29x SoC support

[Andy Fleming]

On Wed, Apr 24, 2013 at 2:14 AM, Po Liu <Po.Liu at freescale.com> wrote:

> From: Mingkai Hu <Mingkai.Hu at freescale.com>
>
> The Freescale C29x family is a high performance crypto co-processor.
> It combines a single e500v2 core with necessary SEC engine. There're
> three SoC types(C291, C292, C293) with the following features:
>
>  - 512K L2 Cache/SRAM and 512 KB platform SRAM
>  - DDR3/DDR3L 32bit DDR controller
>  - One PCI express (x1, x2, x4) Gen 2.0 Controller
>  - Trust Architecture 2.0
>  - SEC6.0 engine
>

[...]


> diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c
> b/arch/powerpc/cpu/mpc8xxx/cpu.c
> index 39525fb..478a852 100644
> --- a/arch/powerpc/cpu/mpc8xxx/cpu.c
> +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
> @@ -88,6 +88,9 @@ static struct cpu_type cpu_type_list[] = {
>         CPU_TYPE_ENTRY(BSC9131, 9131, 1),
>         CPU_TYPE_ENTRY(BSC9132, 9132, 2),
>         CPU_TYPE_ENTRY(BSC9232, 9232, 2),
> +       CPU_TYPE_ENTRY(C291, C291, 1),
> +       CPU_TYPE_ENTRY(C292, C292, 1),
> +       CPU_TYPE_ENTRY(C293, C293, 1),
>  #elif defined(CONFIG_MPC86xx)
>         CPU_TYPE_ENTRY(8610, 8610, 1),
>         CPU_TYPE_ENTRY(8641, 8641, 2),
> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
> b/arch/powerpc/include/asm/config_mpc85xx.h
> index d57c178..0ec0940 100644
> --- a/arch/powerpc/include/asm/config_mpc85xx.h
> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> @@ -587,6 +587,26 @@
>  #define CONFIG_SYS_FSL_ERRATUM_A_004934
>  #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
>
> +#elif defined(CONFIG_C29X)
> +#define CONFIG_MAX_CPUS                        1
> +#define CONFIG_FSL_SDHC_V2_3
> +#define CONFIG_SYS_FSL_NUM_LAWS                12
> +#define CONFIG_SYS_PPC_E500_DEBUG_TLB  3
> +#define CONFIG_TSECV2_1
> +#define CONFIG_SYS_FSL_SEC_COMPAT      6
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> +#define CONFIG_NUM_DDR_CONTROLLERS     1
> +#define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
> +#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
> +
> +#if defined(CONFIG_C293)
> +#define CONFIG_SYS_FSL_SEC_NUM         3
> +#elif defined(CONFIG_C292)
> +#define CONFIG_SYS_FSL_SEC_NUM         2
> +#elif defined(CONFIG_C291)
> +#define CONFIG_SYS_FSL_SEC_NUM         1
> +#endif
>

Could you find a different way to do this? It's a bit absurd that we have
to have 3 different build targets for devices which are the same (from the
point of view of u-boot) except for this one constant. Especially since the
variant can be determined at run-time via SVR. Also, CONFIG_SYS_FSL_SEC_NUM
doesn't appear to be used anywhere...

Andy