[U-Boot] [PATCH v5 1/8] ARM: dove: add support for Marvell Dove SoC

[Sebastian Hesselbarth]

On 06/25/2013 11:27 PM, Sascha Silbe wrote:
> This patch adds initial support for the armv7-based Marvell Dove SoC
> (88AP510).
>
> Signed-off-by: Sascha Silbe<t-uboot at infra-silbe.de>
> ---
> v4->v5: some adjustments for the GPIO and SPI driver changes
>
[...]
> diff --git a/arch/arm/include/asm/arch-dove/config.h b/arch/arm/include/asm/arch-dove/config.h
> new file mode 100644
> index 0000000..38bf6ce
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/config.h
> @@ -0,0 +1,153 @@
> +/*
> + * Marvell SoC config
> + *
> + * Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_CONFIG_H
> +#define _DOVE_CONFIG_H
> +
> +#include<asm/arch/dove.h>
> +
> +#define CONFIG_ARMV7			/* Basic Architecture */
> +#define CONFIG_DOVE			/* SOC Family Name */
> +#define CONFIG_SHEEVA_88SV581		/* CPU Core subversion */
> +#define CONFIG_SYS_CACHELINE_SIZE	32
> +				/* default Dcache Line length for Dove */
> +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
> +#define CONFIG_SYS_DCACHE_OFF		/* Disable DCache by default */
> +
> +/*
> + * By default kwbimage.cfg from board specific folder is used
> + * If for some board, different configuration file need to be used,
> + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
> + */
> +#ifndef CONFIG_SYS_KWD_CONFIG
> +#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
> +#endif /* CONFIG_SYS_KWD_CONFIG */
> +
> +/* Dove has 2k of Security SRAM, use it for SP */
> +#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000

Actually, DOVE_DEFADR_SASRAM remaps security SRAM to 0xc8000000. Maybe
it just works because addresses are wrapped around each 2k bytes.

I suggest to set the above to 0xc8000800 or use
(DOVE_DEFADR_SASRAM | 0x800)

> +#define CONFIG_NR_DRAM_BANKS_MAX	2
> +
> +#define CONFIG_I2C_MVTWSI_BASE	DOVE_TWSI_BASE
> +#define MV_UART_CONSOLE_BASE	DOVE_UART0_BASE
> +#define MV_SATA_BASE		DOVE_SATA_BASE
> +#define MV_SATA_PORT0_OFFSET	DOVE_SATA_PORT0_OFFSET
> +
> +/*
> + * NAND configuration
> + */
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_NAND_KIRKWOOD		1
> +#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
> +#define NAND_ALLOW_ERASE_ALL		1
> +#endif

Knowing the SoC now better, I can say that NAND controller is kind of
different from Kirkwood. Especially, the above NAND_BASE relies on a
proper address window remap that is not done yet on Dove init code.

I suggest to remove the whole NAND ifdef above until proper NAND
driver is available.

[...]
> +/* CONFIG_CMD_IDE requires some #defines for ATA registers */
> +#define CONFIG_SYS_IDE_MAXBUS		2
> +#define CONFIG_SYS_IDE_MAXDEVICE	2

Dove SoC only has a single SATA port, so I guess above defines should
be set to 1.

[...]
> diff --git a/arch/arm/include/asm/arch-dove/cpu.h b/arch/arm/include/asm/arch-dove/cpu.h
> new file mode 100644
> index 0000000..718dd59
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/cpu.h
> @@ -0,0 +1,204 @@
> +/*
> + * Marvell Dove SoC CPU
> + *
> + * Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVECPU_H
> +#define _DOVECPU_H
> +
> +#include<asm/system.h>
> +
> +#ifndef __ASSEMBLY__
> +
> +#define DOVECPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target<<  4) \
> +			| (attr<<  8) | (dove_winctrl_calcsize(size)<<  16))
> +
> +#define DOVEGBE_PORT_SERIAL_CONTROL1_REG	(DOVE_EGIGA_BASE + 0x44c)
> +#define DOVE_REG_PCIE_DEVID			(DOVE_REG_PCIE0_BASE + 0x00)
> +#define DOVE_REG_PCIE_REVID			(DOVE_REG_PCIE0_BASE + 0x08)
> +#define DOVE_REG_SYSRST_CNT			(DOVE_MPP_BASE + 0x50)
> +#define SYSRST_CNT_1SEC_VAL			(25*1000000)

Wherever the above is used or from, don't ask me why I came up with it. 
Dove has no register to set sysrst_out length.

[...]
> diff --git a/arch/arm/include/asm/arch-dove/dove.h b/arch/arm/include/asm/arch-dove/dove.h
> new file mode 100644
> index 0000000..f310719
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-dove/dove.h
> @@ -0,0 +1,98 @@
> +/*
> + * Marvell Dove SoC register offsets and config
> + *
> + * Sebastian Hesselbarth<sebastian.hesselbarth at gmail.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _DOVE_H
> +#define _DOVE_H
> +
> +/* Dove TCLK is fixed to 166MHz */
> +#define CONFIG_SYS_TCLK			166666667

Not entirely true as it is configurable by SAR registers. The only
two frequencies allowed are 125MHz and 166MHz above. This is what is
given in Dove FS, but there may be other possible (undocumented)
frequencies.

[...]
> +#define DOVE_SPI_BASE			(DOVE_REGISTER(0x10600))

DOVE_SPI0_BASE and add DOVE_SPI1_BASE at 0x14600.

> +#define DOVE_TWSI_BASE			(DOVE_REGISTER(0x11000))
> +#define DOVE_UART0_BASE			(DOVE_REGISTER(0x12000))
> +#define DOVE_UART1_BASE			(DOVE_REGISTER(0x12100))
> +#define DOVE_UART2_BASE			(DOVE_REGISTER(0x12200))
> +#define DOVE_UART3_BASE			(DOVE_REGISTER(0x12300))
> +#define DOVE_CPU_WIN_BASE		(DOVE_REGISTER(0x20000))
> +#define DOVE_CPU_REG_BASE		(DOVE_REGISTER(0x20100))
> +#define DOVE_TIMER_BASE			(DOVE_REGISTER(0x20300))
> +#define DOVE_REG_PCIE0_BASE		(DOVE_REGISTER(0x40000))
> +#define DOVE_REG_PCIE1_BASE		(DOVE_REGISTER(0x80000))

Out of curiosity, is the board you are planing to add support for
equipped with PCIe slots or anything connected to PCIe?

Thanks for giving the patch set a re-spin.

Sebastian