[U-Boot] [Patch v2, batch 4 20/29] powerpc/doc: Fix the misalignment of document README.srio-pcie-boot-corenet

[York Sun]

From: Liu Gang <Gang.Liu at freescale.com>

Misalignment will be found in the doc/README.srio-pcie-boot-corenet
file when the tabs are set to 8 characters. And the standard for u-boot
should be 8 character tabs!

Signed-off-by: Liu Gang <Gang.Liu at freescale.com>
---
 doc/README.srio-pcie-boot-corenet |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet
index cd7e7ee..7e68174 100644
--- a/doc/README.srio-pcie-boot-corenet
+++ b/doc/README.srio-pcie-boot-corenet
@@ -21,13 +21,13 @@ Environment of the SRIO or PCIE boot:
 	e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
 	   the boot location to SRIO or PCIE, and holdoff all the cores.
 
-	----------        -----------             -----------
-	|		  |       |         |             |         |
-	|		  |       |         |             |         |
+	-----------       -----------             -----------
+	|         |       |         |             |         |
+	|         |       |         |             |         |
 	| NorFlash|<----->| Master  |SRIO or PCIE |  Slave  |<---->[EEPROM]
-	|		  |       |         |<===========>|         |
-	|		  |       |         |             |         |
-	----------        -----------             -----------
+	|         |       |         |<===========>|         |
+	|         |       |         |             |         |
+	-----------       -----------             -----------
 
 The example based on P4080DS platform:
 	Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
-- 
1.7.9.5