[U-Boot] [PATCH 5/8] Add TI816X cpu definitions

TENART Antoine atenart at adeneo-embedded.com
Thu Mar 28 18:14:38 CET 2013


---
 arch/arm/include/asm/arch-am33xx/cpu.h        |    4 +
 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h |  269 +++++++++++++++++++++++++
 arch/arm/include/asm/emif.h                   |    4 +
 3 files changed, 277 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 13c0667..34b3aa9 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -25,6 +25,10 @@
 
 #include <asm/arch/hardware.h>
 
+#if defined(CONFIG_TI816X)
+#include <asm/arch/cpu_ti816x.h>
+#endif
+
 #define BIT(x)				(1 << x)
 #define CL_BIT(x)			(0 << x)
 
diff --git a/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
new file mode 100644
index 0000000..b4a13a8
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h
@@ -0,0 +1,269 @@
+/*
+ * cpu_ti816x.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart at adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * (C) Copyright 2006
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _TI816X_CPU_H
+#define _TI816X_CPU_H
+
+#include <asm/arch/hardware.h>
+
+/* Timer registers */
+#define TIMER_TCLR			0x38		/* Timer control register */
+#define TIMER_TCRR			0x3C		/* Timer counter register */
+#define TIMER_TLDR			0x40		/* Timer load value register*/
+
+/* Control */
+#define CONTROL_STATUS		(CTRL_BASE + 0x40)
+
+/* device type */
+#define DEVICE_MASK			(BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE			0x0
+#define EMU_DEVICE			0x1
+#define HS_DEVICE			0x2
+#define GP_DEVICE			0x3
+
+/* This gives the buswidth of the booting device */
+#define SYSBOOT_BW_POS		(16)
+#define SYSBOOT_BW_MASK		(BIT(SYSBOOT_BW_POS))
+
+/* Reset control */
+#define PRM_DEVICE_RSTCTRL	(PRCM_BASE + 0x00A0)
+
+/* TI816X specific bits for PRM_DEVICE module */
+#define GLOBAL_RST_COLD		BIT(1)
+
+/* PLL related registers */
+#define MAINPLL_CTRL		(CTRL_BASE + 0x0400)
+#define MAINPLL_PWD			(CTRL_BASE + 0x0404)
+#define MAINPLL_FREQ1		(CTRL_BASE + 0x0408)
+#define MAINPLL_DIV1		(CTRL_BASE + 0x040C)
+#define MAINPLL_FREQ2		(CTRL_BASE + 0x0410)
+#define MAINPLL_DIV2		(CTRL_BASE + 0x0414)
+#define MAINPLL_FREQ3		(CTRL_BASE + 0x0418)
+#define MAINPLL_DIV3		(CTRL_BASE + 0x041C)
+#define MAINPLL_FREQ4		(CTRL_BASE + 0x0420)
+#define MAINPLL_DIV4		(CTRL_BASE + 0x0424)
+#define MAINPLL_FREQ5		(CTRL_BASE + 0x0428)
+#define MAINPLL_DIV5		(CTRL_BASE + 0x042C)
+#define MAINPLL_DIV6		(CTRL_BASE + 0x0434)
+#define MAINPLL_DIV7		(CTRL_BASE + 0x043C)
+
+#define DDRPLL_CTRL			(CTRL_BASE + 0x0440)
+#define DDRPLL_PWD			(CTRL_BASE + 0x0444)
+#define DDRPLL_DIV1			(CTRL_BASE + 0x044C)
+#define DDRPLL_FREQ2		(CTRL_BASE + 0x0450)
+#define DDRPLL_DIV2			(CTRL_BASE + 0x0454)
+#define DDRPLL_FREQ3		(CTRL_BASE + 0x0458)
+#define DDRPLL_DIV3			(CTRL_BASE + 0x045C)
+#define DDRPLL_FREQ4		(CTRL_BASE + 0x0460)
+#define DDRPLL_DIV4			(CTRL_BASE + 0x0464)
+#define DDRPLL_FREQ5		(CTRL_BASE + 0x0468)
+#define DDRPLL_DIV5			(CTRL_BASE + 0x046C)
+
+#define DDR_RCD				(CTRL_BASE + 0x070C)
+
+#define VIDEOPLL_CTRL		(CTRL_BASE + 0x0470)
+#define VIDEOPLL_PWD		(CTRL_BASE + 0x0474)
+#define VIDEOPLL_FREQ1		(CTRL_BASE + 0x0478)
+#define VIDEOPLL_DIV1		(CTRL_BASE + 0x047C)
+#define VIDEOPLL_FREQ2		(CTRL_BASE + 0x0480)
+#define VIDEOPLL_DIV2		(CTRL_BASE + 0x0484)
+#define VIDEOPLL_FREQ3		(CTRL_BASE + 0x0488)
+#define VIDEOPLL_DIV3		(CTRL_BASE + 0x048C)
+
+#define AUDIOPLL_CTRL		(CTRL_BASE + 0x04A0)
+#define AUDIOPLL_PWD		(CTRL_BASE + 0x04A4)
+#define AUDIOPLL_FREQ2		(CTRL_BASE + 0x04B0)
+#define AUDIOPLL_DIV2		(CTRL_BASE + 0x04B4)
+#define AUDIOPLL_FREQ3		(CTRL_BASE + 0x04B8)
+#define AUDIOPLL_DIV3		(CTRL_BASE + 0x04BC)
+#define AUDIOPLL_FREQ4		(CTRL_BASE + 0x04C0)
+#define AUDIOPLL_DIV4		(CTRL_BASE + 0x04C4)
+#define AUDIOPLL_FREQ5		(CTRL_BASE + 0x04C8)
+#define AUDIOPLL_DIV5		(CTRL_BASE + 0x04CC)
+
+/* PRCM */
+#define CM_DPLL_OFFSET		(PRCM_BASE + 0x0300)
+
+#ifdef CONFIG_TI816X
+#define CM_TIMER1_CLKSEL	(CM_DPLL_OFFSET + 0x90)
+
+/* Timers */
+#define CM_ALWON_TIMER_0_CLKCTRL	(PRCM_BASE + 0x156C)
+#define CM_ALWON_TIMER_1_CLKCTRL	(PRCM_BASE + 0x1570)
+#define CM_ALWON_TIMER_2_CLKCTRL	(PRCM_BASE + 0x1574)
+#define CM_ALWON_TIMER_3_CLKCTRL	(PRCM_BASE + 0x1578)
+#define CM_ALWON_TIMER_4_CLKCTRL	(PRCM_BASE + 0x157C)
+#define CM_ALWON_TIMER_5_CLKCTRL	(PRCM_BASE + 0x1580)
+#define CM_ALWON_TIMER_6_CLKCTRL	(PRCM_BASE + 0x1584)
+#define CM_ALWON_TIMER_7_CLKCTRL	(PRCM_BASE + 0x1588)
+#endif
+
+#define CM_ALWON_WDTIMER_CLKCTRL	(PRCM_BASE + 0x158C)
+#define CM_ALWON_SPI_CLKCTRL		(PRCM_BASE + 0x1590)
+#define CM_ALWON_CONTROL_CLKCTRL	(PRCM_BASE + 0x15C4)
+
+#define CM_ALWON_L3_SLOW_CLKSTCTRL	(PRCM_BASE + 0x1400)
+
+#ifdef CONFIG_TI816X
+#define CM_ALWON_CUST_EFUSE_CLKCTRL	(PRCM_BASE + 0x1628)
+#endif
+
+#define CM_ALWON_GPIO_0_CLKCTRL		(PRCM_BASE + 0x155c)
+#define CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK (PRCM_BASE + 0x155c)
+
+#define CM_ALWON_GPIO_1_CLKCTRL		(PRCM_BASE + 0x1560)
+/* Ethernet */
+#define CM_ETHERNET_CLKSTCTRL		(PRCM_BASE + 0x1404)
+#define CM_ALWON_ETHERNET_0_CLKCTRL	(PRCM_BASE + 0x15D4)
+#define CM_ALWON_ETHERNET_1_CLKCTRL	(PRCM_BASE + 0x15D8)
+
+/* UARTs */
+#define CM_ALWON_UART_0_CLKCTRL		(PRCM_BASE + 0x1550)
+#define CM_ALWON_UART_1_CLKCTRL		(PRCM_BASE + 0x1554)
+#define CM_ALWON_UART_2_CLKCTRL		(PRCM_BASE + 0x1558)
+
+/* I2C */
+/* Note: In ti814x I2C0 and I2C2 have common clk control */
+#define CM_ALWON_I2C_0_CLKCTRL		(PRCM_BASE + 0x1564)
+
+/* HSMMC */
+#ifdef CONFIG_TI816X
+#define CM_ALWON_HSMMC_CLKCTRL		(PRCM_BASE + 0x15B0)
+#endif
+
+/* UART registers */
+#define UART_SYSCFG			(DEFAULT_UART_BASE + 0x54)
+#define UART_SYSSTS			(DEFAULT_UART_BASE + 0x58)
+#define UART_LCR			(DEFAULT_UART_BASE + 0x0C)
+#define UART_EFR			(DEFAULT_UART_BASE + 0x08)
+#define UART_MCR			(DEFAULT_UART_BASE + 0x10)
+#define UART_SCR			(DEFAULT_UART_BASE + 0x40)
+#define UART_TCR			(DEFAULT_UART_BASE + 0x18)
+#define UART_FCR			(DEFAULT_UART_BASE + 0x08)
+#define UART_DLL			(DEFAULT_UART_BASE + 0x00)
+#define UART_DLH			(DEFAULT_UART_BASE + 0x04)
+#define UART_MDR			(DEFAULT_UART_BASE + 0x20)
+
+/*DMM & EMIF4 MMR Declaration*/
+#define DMM_LISA_MAP__0			(DMM_BASE + 0x40)
+#define DMM_LISA_MAP__1			(DMM_BASE + 0x44)
+#define DMM_LISA_MAP__2			(DMM_BASE + 0x48)
+#define DMM_LISA_MAP__3			(DMM_BASE + 0x4C)
+#define DMM_PAT_BASE_ADDR		(DMM_BASE + 0x460)
+
+#define EMIF4_0_SDRAM_ZQCR				(EMIF4_0_CFG_BASE + 0xC8)
+#define EMIF4_0_SDRAM_CONFIG			(EMIF4_0_CFG_BASE + 0x08)
+#define EMIF4_0_SDRAM_CONFIG2			(EMIF4_0_CFG_BASE + 0x0C)
+#define EMIF4_0_SDRAM_REF_CTRL			(EMIF4_0_CFG_BASE + 0x10)
+#define EMIF4_0_SDRAM_REF_CTRL_SHADOW	(EMIF4_0_CFG_BASE + 0x14)
+#define EMIF4_0_SDRAM_TIM_1				(EMIF4_0_CFG_BASE + 0x18)
+#define EMIF4_0_SDRAM_TIM_1_SHADOW		(EMIF4_0_CFG_BASE + 0x1C)
+#define EMIF4_0_SDRAM_TIM_2				(EMIF4_0_CFG_BASE + 0x20)
+#define EMIF4_0_SDRAM_TIM_2_SHADOW		(EMIF4_0_CFG_BASE + 0x24)
+#define EMIF4_0_SDRAM_TIM_3				(EMIF4_0_CFG_BASE + 0x28)
+#define EMIF4_0_SDRAM_TIM_3_SHADOW		(EMIF4_0_CFG_BASE + 0x2C)
+#define EMIF4_0_DDR_PHY_CTRL_1			(EMIF4_0_CFG_BASE + 0xE4)
+#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW	(EMIF4_0_CFG_BASE + 0xE8)
+#define EMIF4_0_IODFT_TLGC				(EMIF4_0_CFG_BASE + 0x60)
+
+#define EMIF4_1_SDRAM_ZQCR				(EMIF4_1_CFG_BASE + 0xC8)
+#define EMIF4_1_SDRAM_CONFIG			(EMIF4_1_CFG_BASE + 0x08)
+#define EMIF4_1_SDRAM_CONFIG2			(EMIF4_1_CFG_BASE + 0x0C)
+#define EMIF4_1_SDRAM_REF_CTRL			(EMIF4_1_CFG_BASE + 0x10)
+#define EMIF4_1_SDRAM_REF_CTRL_SHADOW	(EMIF4_1_CFG_BASE + 0x14)
+#define EMIF4_1_SDRAM_TIM_1				(EMIF4_1_CFG_BASE + 0x18)
+#define EMIF4_1_SDRAM_TIM_1_SHADOW		(EMIF4_1_CFG_BASE + 0x1C)
+#define EMIF4_1_SDRAM_TIM_2				(EMIF4_1_CFG_BASE + 0x20)
+#define EMIF4_1_SDRAM_TIM_2_SHADOW		(EMIF4_1_CFG_BASE + 0x24)
+#define EMIF4_1_SDRAM_TIM_3				(EMIF4_1_CFG_BASE + 0x28)
+#define EMIF4_1_SDRAM_TIM_3_SHADOW		(EMIF4_1_CFG_BASE + 0x2C)
+#define EMIF4_1_DDR_PHY_CTRL_1			(EMIF4_1_CFG_BASE + 0xE4)
+#define EMIF4_1_DDR_PHY_CTRL_1_SHADOW	(EMIF4_1_CFG_BASE + 0xE8)
+#define EMIF4_1_IODFT_TLGC				(EMIF4_1_CFG_BASE + 0x60)
+
+/*EMIF4 PRCM Defintion*/
+#define CM_DEFAULT_L3_FAST_CLKSTCTRL	(PRCM_BASE + 0x0508)
+#define CM_DEFAULT_EMIF_0_CLKCTRL		(PRCM_BASE + 0x0520)
+#define CM_DEFAULT_EMIF_1_CLKCTRL		(PRCM_BASE + 0x0524)
+#define CM_DEFAULT_DMM_CLKCTRL			(PRCM_BASE + 0x0528)
+#define CM_DEFAULT_FW_CLKCTRL			(PRCM_BASE + 0x052C)
+
+/* Smartreflex Registers */
+#define TI816X_SMRT_SCALE_ADDR		(CTRL_BASE + 0x06A0)
+#define TI816X_SMRT_OPP_SVT_ADDR	(CTRL_BASE + 0x06A8)
+#define TI816X_SMRT_OPP_HVT_ADDR	(CTRL_BASE + 0x06AC)
+
+
+/* ALWON PRCM */
+#define CM_ALWON_OCMC_0_CLKSTCTRL	(PRCM_BASE + 0x1414)
+#define CM_ALWON_OCMC_0_CLKCTRL		(PRCM_BASE + 0x15B4)
+#define CM_ALWON_OCMC_1_CLKSTCTRL	(PRCM_BASE + 0x1418)
+#define CM_ALWON_OCMC_1_CLKCTRL		(PRCM_BASE + 0x15B8)
+
+#define CM_ALWON_GPMC_CLKCTRL		(PRCM_BASE + 0x15D0)
+
+/* OCMC */
+#define SRAM0_SIZE				(0x40000)
+#define SRAM_GPMC_STACK_SIZE	(0x40)
+
+/* GPMC related */
+#define GPMC_CONFIG_CS0			(0x60)
+#define GPMC_CONFIG_CS0_BAS		(GPMC_BASE + GPMC_CONFIG_CS0)
+#define GPMC_CONFIG1			(0x00)
+#define GPMC_CONFIG2			(0x04)
+#define GPMC_CONFIG3			(0x08)
+#define GPMC_CONFIG4			(0x0C)
+#define GPMC_CONFIG5			(0x10)
+#define GPMC_CONFIG6			(0x14)
+#define GPMC_CONFIG7			(0x18)
+
+/* WDT related */
+#define WDT_WDSC		(WDT_BASE + 0x010)
+#define WDT_WDST		(WDT_BASE + 0x014)
+#define WDT_WISR		(WDT_BASE + 0x018)
+#define WDT_WIER		(WDT_BASE + 0x01C)
+#define WDT_WWER		(WDT_BASE + 0x020)
+#define WDT_WCLR		(WDT_BASE + 0x024)
+#define WDT_WCRR		(WDT_BASE + 0x028)
+#define WDT_WLDR		(WDT_BASE + 0x02C)
+#define WDT_WTGR		(WDT_BASE + 0x030)
+#define WDT_WWPS		(WDT_BASE + 0x034)
+#define WDT_WDLY		(WDT_BASE + 0x044)
+#define WDT_WSPR		(WDT_BASE + 0x048)
+#define WDT_WIRQEOI		(WDT_BASE + 0x050)
+#define WDT_WIRQSTATRAW	(WDT_BASE + 0x054)
+#define WDT_WIRQSTAT	(WDT_BASE + 0x058)
+#define WDT_WIRQENSET	(WDT_BASE + 0x05C)
+#define WDT_WIRQENCLR	(WDT_BASE + 0x060)
+
+#define WDT_UNFREEZE	(CTRL_BASE + 0x100)
+
+#endif /* _TI816X_CPU_H */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index ed251ec..a7b938c 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -521,7 +521,11 @@
 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES	0x000001A7
 
 /* DMM */
+#if defined(CONFIG_TI816X)
+#define DMM_BASE			0x4E000000
+#else
 #define DMM_BASE			0x4E000040
+#endif
 
 /* Memory Adapter */
 #define MA_BASE				0x482AF040
-- 
1.7.10.4


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