[U-Boot] [PATCH 6/8] Add TI816X specific register definitions

[TENART Antoine]

Also move some non common defintions from hardware.h
---
 arch/arm/include/asm/arch-am33xx/hardware.h        |    7 +--
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |    5 ++
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |    5 ++
 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h |   58 ++++++++++++++++++++
 4 files changed, 70 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h

diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 5a27f9c..7f3b555 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -23,6 +23,8 @@
 #include <asm/arch/omap.h>
 #ifdef CONFIG_AM33XX
 #include <asm/arch/hardware_am33xx.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/hardware_ti816x.h>
 #elif defined(CONFIG_TI814X)
 #include <asm/arch/hardware_ti814x.h>
 #endif
@@ -67,15 +69,10 @@
 /* DDR Base address */
 #define DDR_CTRL_ADDR			0x44E10E04
 #define DDR_CONTROL_BASE_ADDR		0x44E11404
-#define DDR_PHY_CMD_ADDR2		0x47C0C800
-#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
 
 /* UART */
 #define DEFAULT_UART_BASE		UART0_BASE
 
-#define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
-#define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
-
 /* GPMC Base address */
 #define GPMC_BASE			0x50000000
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index fa02f19..49a4392 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -43,8 +43,13 @@
 /* DDR Base address */
 #define DDR_PHY_CMD_ADDR		0x44E12000
 #define DDR_PHY_DATA_ADDR		0x44E120C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
 #define DDR_DATA_REGS_NR		2
 
+#define DDRPHY_0_CONFIG_BASE    (CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE      DDRPHY_0_CONFIG_BASE
+
 /* CPSW Config space */
 #define CPSW_MDIO_BASE			0x4A101000
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
index a950ac3..ae0f370 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -42,8 +42,13 @@
 /* DDR Base address */
 #define DDR_PHY_CMD_ADDR		0x47C0C400
 #define DDR_PHY_DATA_ADDR		0x47C0C4C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
 #define DDR_DATA_REGS_NR		4
 
+#define DDRPHY_0_CONFIG_BASE	(CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
+
 /* CPSW Config space */
 #define CPSW_MDIO_BASE			0x4A100800
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
new file mode 100644
index 0000000..cb75d09
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
@@ -0,0 +1,58 @@
+/*
+ * hardware_ti816x.h
+ *
+ * TI816x hardware specific header
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart at adeneo-embedded.com>
+ * Based on TI-PSP-04.00.02.14
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_TI816X_H
+#define __AM33XX_HARDWARE_TI816X_H
+
+/* Watchdog Timer */
+#define WDT_BASE				0x480C2000
+
+/* Control Module Base Address */
+#define CTRL_BASE				0x48140000
+
+/* PRCM Base Address */
+#define PRCM_BASE				0x48180000
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x48198358
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x48198000
+#define DDR_PHY_DATA_ADDR		0x481980C8
+#define DDR_PHY_CMD_ADDR2		0x4819A000
+#define DDR_PHY_DATA_ADDR2		0x4819A0C8
+#define DDR_DATA_REGS_NR		4
+
+/* UART */
+#define UART0_BASE				0x48020000
+#define UART1_BASE				0x48022000
+#define UART2_BASE				0x48024000
+
+#define DDRPHY_0_CONFIG_BASE	0x48198000
+#define DDRPHY_1_CONFIG_BASE	0x4819a000
+#define DDRPHY_CONFIG_BASE		((emif == 0) ? DDRPHY_0_CONFIG_BASE:DDRPHY_1_CONFIG_BASE)
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A100800
+
+/* RTC base address */
+#define RTC_BASE				0x480C0000
+
+#endif /* __AM33XX_HARDWARE_TI816X_H */
-- 
1.7.10.4