[U-Boot] [PATCH] mx6: Add initial support for Carrier1 mx6solo board

Fabio Estevam festevam at gmail.com
Sat Nov 2 19:41:25 CET 2013


From: Fabio Estevam <fabio.estevam at freescale.com>

Solid Run designed the Carrier1 board based on mx6q/dl/solo.

Add the initial support for the mx6 solo variant.

More information about this hardware can be found at:
http://cubox-i.com/

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 board/solidrun/carrier1/800mhz_2x256mx16.cfg       |  74 +++++++
 board/solidrun/carrier1/Makefile                   |  26 +++
 board/solidrun/carrier1/README                     |  35 ++++
 board/solidrun/carrier1/carrier1.c                 | 197 ++++++++++++++++++
 board/solidrun/carrier1/clocks.cfg                 |  33 +++
 board/solidrun/carrier1/ddr-800mhz-32bit-setup.cfg |  67 ++++++
 board/solidrun/carrier1/mx6_c1solo.cfg             |  25 +++
 boards.cfg                                         |   3 +
 include/configs/carrier1.h                         | 227 +++++++++++++++++++++
 9 files changed, 687 insertions(+)
 create mode 100644 board/solidrun/carrier1/800mhz_2x256mx16.cfg
 create mode 100644 board/solidrun/carrier1/Makefile
 create mode 100644 board/solidrun/carrier1/README
 create mode 100644 board/solidrun/carrier1/carrier1.c
 create mode 100644 board/solidrun/carrier1/clocks.cfg
 create mode 100644 board/solidrun/carrier1/ddr-800mhz-32bit-setup.cfg
 create mode 100644 board/solidrun/carrier1/mx6_c1solo.cfg
 create mode 100644 include/configs/carrier1.h

diff --git a/board/solidrun/carrier1/800mhz_2x256mx16.cfg b/board/solidrun/carrier1/800mhz_2x256mx16.cfg
new file mode 100644
index 0000000..c0398f0
--- /dev/null
+++ b/board/solidrun/carrier1/800mhz_2x256mx16.cfg
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton at gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ZQ Calibrations */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
+/* write leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x000F0011
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E000F
+/*
+ * DQS gating, read delay, write delay calibration values
+ * based on calibration compare of 0x00ffff00
+ */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42240229
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021a0219
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4e4f5150
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35363136
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+/* Complete calibration by forced measurement */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/*
+ * MMDC init:
+ * in DDR3, 32-bit mode, only MMDC0 is initiated:
+ */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xb68e8c63
+
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
+/* CS0_END - 0x2fffffff, 512M  */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+
+/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */
+DATA 4, 0x021b0400, 0x11420000
+
+/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+
+/*
+ * Initialize 2GB DDR3 - Micron MT41J128M
+ * MR2
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+/* MR3 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+/* MR1 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+/* MR0 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+/* final DDR setup */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/solidrun/carrier1/Makefile b/board/solidrun/carrier1/Makefile
new file mode 100644
index 0000000..a18451e
--- /dev/null
+++ b/board/solidrun/carrier1/Makefile
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2013, Jon Nettleton <jon.nettleton at gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := carrier1.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/solidrun/carrier1/README b/board/solidrun/carrier1/README
new file mode 100644
index 0000000..89d0aa0
--- /dev/null
+++ b/board/solidrun/carrier1/README
@@ -0,0 +1,35 @@
+U-Boot for Solid Run Carrier1
+-----------------------------
+
+This file contains information for the port of U-Boot to the Carrier1 board.
+
+For more details about Carrier1, please refer to:
+http://cubox-i.com
+
+Building U-boot for Carrier1
+----------------------------
+
+To build U-Boot for the Carrier1 Solo version:
+
+$ make carrier1_solo_config
+$ make
+
+Flashing U-boot into the SD card
+--------------------------------
+
+- After the 'make' command completes, the generated 'u-boot.imx' binary must be
+flashed into the SD card:
+
+$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=1k seek=1; sync
+
+(Note - the SD card node may vary, so adjust this as needed).
+
+- Insert the micro SD card into the slot located in the bottom of the board
+
+- Connect a 3.3V USB to serial converter cable to the host PC. The MX6 UART
+signals are available in the 26 pin connector as shown at:
+http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
+(Check for "26 pin header layout").
+
+- Power up the board via USB cable (CON201) and U-boot messages will appear in
+the serial console.
diff --git a/board/solidrun/carrier1/carrier1.c b/board/solidrun/carrier1/carrier1.c
new file mode 100644
index 0000000..9c4ec49
--- /dev/null
+++ b/board/solidrun/carrier1/carrier1.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton at gmail.com>.
+ *
+ * Author: Fabio Estevam <fabio.estevam at freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW |			\
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST |			\
+	PAD_CTL_HYS)
+
+#define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP |		\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ETH_PHY_RESET	IMX_GPIO_NR(4, 15)
+
+int dram_init(void)
+{
+	gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{ USDHC2_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1; /* SD card is the boot medium, so always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* AR8035 reset */
+	MX6_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+	/* AR8035 interrupt */
+	MX6_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* GPIO16 -> AR8035 25MHz */
+	MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+	/* Reset AR8035 PHY */
+	gpio_direction_output(ETH_PHY_RESET, 0);
+	udelay(1000 * 2);    /* Wait 2 ms before reset */
+	gpio_set_value(ETH_PHY_RESET, 1);
+
+	udelay(100);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+	struct iomuxc_base_regs *iomuxc_regs = (struct iomuxc_base_regs *)
+						IOMUXC_BASE_ADDR;
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	s32 timeout = 100000;
+
+	u32 reg = readl(&anatop->pll_enet);
+	reg |= 0x00002000;
+	writel(reg, &anatop->pll_enet);
+
+	/* clear gpr1[21] */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], (1 << 21), 1);
+
+	while (timeout--) {
+		if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
+			break;
+	}
+
+	setup_iomux_enet();
+
+	ret = cpu_eth_init(bis);
+	if (ret)
+		printf("FEC MXC: %s:failed: %d\n", __func__, ret);
+
+	return ret;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6 Carrier1\n");
+
+	return 0;
+}
diff --git a/board/solidrun/carrier1/clocks.cfg b/board/solidrun/carrier1/clocks.cfg
new file mode 100644
index 0000000..1288811
--- /dev/null
+++ b/board/solidrun/carrier1/clocks.cfg
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton at gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1    --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/solidrun/carrier1/ddr-800mhz-32bit-setup.cfg b/board/solidrun/carrier1/ddr-800mhz-32bit-setup.cfg
new file mode 100644
index 0000000..f89a296
--- /dev/null
+++ b/board/solidrun/carrier1/ddr-800mhz-32bit-setup.cfg
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton at gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+/*
+ * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS,
+ * CMOS mode saves power, but have less timing margin in case of DDR
+ * timing issue on your board you can try DDR_MODE:  [= 0x00020000]
+ */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00000000
+
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
+
+/*
+ * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS,
+ * CMOS mode saves power, but have less timing margin in case of DDR
+ * timing issue on your board you can try DDR_MODE:  [= 0x00020000]
+ */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00000000
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
diff --git a/board/solidrun/carrier1/mx6_c1solo.cfg b/board/solidrun/carrier1/mx6_c1solo.cfg
new file mode 100644
index 0000000..1acad07
--- /dev/null
+++ b/board/solidrun/carrier1/mx6_c1solo.cfg
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton at gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-800mhz-32bit-setup.cfg"
+#include "800mhz_2x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/boards.cfg b/boards.cfg
index cec154b..892973a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -306,6 +306,9 @@ Active  arm         armv7          mx6         freescale       mx6sabresd
 Active  arm         armv7          mx6         freescale       mx6sabresd          mx6qsabresd                          mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q                                                           Fabio Estevam <fabio.estevam at freescale.com>
 Active  arm         armv7          mx6         freescale       mx6slevk            mx6slevk                             mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL                                                                   Fabio Estevam <fabio.estevam at freescale.com>
 Active  arm         armv7          mx6         freescale       titanium            titanium                             titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg                                                                         Stefan Roese <sr at denx.de>
+
+Active  arm         armv7          mx6         solidrun        carrier1            carrier1_solo                        carrier1:IMX_CONFIG=board/solidrun/carrier1/mx6_c1solo.cfg,MX6S,DDR_MB=512	                                                  Fabio Estevam <fabio.estevam at freescale.com>
+
 Active  arm         armv7          omap3       -               overo               omap3_overo                          -                                                                                                                                 Steve Sakoman <sakoman at gmail.com>
 Active  arm         armv7          omap3       -               pandora             omap3_pandora                        -                                                                                                                                 Grazvydas Ignotas <notasas at gmail.com>
 Active  arm         armv7          omap3       8dtech          eco5pk              eco5pk                               -                                                                                                                                 Raphael Assenat <raph at 8d.com>
diff --git a/include/configs/carrier1.h b/include/configs/carrier1.h
new file mode 100644
index 0000000..969e3ad
--- /dev/null
+++ b/include/configs/carrier1.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton at gmail.com>
+ *
+ * Configuration settings for the SolidRun Carrier1 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <asm/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_CARRIER1		4773
+#define CONFIG_MACH_TYPE		MACH_TYPE_CARRIER1
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(2 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_I2C
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+#if defined(CONFIG_MX6S)
+#define CONFIG_DEFAULT_FDT_FILE		"imx6dl-carrier1.dtb"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"console=ttymxc0\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x11000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loaduimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	       "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H * */
-- 
1.8.1.2



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