[U-Boot] [PATCH 6/6][v2] T1040QDS: Add support of 2 stage NAND boot loader
Scott Wood
scottwood at freescale.com
Wed Nov 6 02:56:54 CET 2013
On Fri, 2013-10-25 at 10:09 +0530, Prabhakar Kushwaha wrote:
> Add support of 2 stage NAND boot loader using SPL framework.
> here, PBL initialise the internal SRAM(256K) and copy SPL(192K). This further
> initialise DDR using SPD and environment and copy u-boot(512 kb) from NAND to DDR.
> Finally SPL transer control to u-boot.
>
> Initialise/create followings required for SPL framework
> - Add spl.c which defines board_init_f, board_init_r
> - update tlb and ddr accordingly
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
> ---
> Based upon git://git.denx.de/u-boot-mpc85xx.git branch next
>
> Changes for v2: sending as it is
>
> board/freescale/t1040qds/Makefile | 9 ++-
> board/freescale/t1040qds/README | 33 ++++++++++
> board/freescale/t1040qds/ddr.c | 7 ++-
> board/freescale/t1040qds/spl.c | 122 +++++++++++++++++++++++++++++++++++++
> board/freescale/t1040qds/tlb.c | 8 ++-
> boards.cfg | 1 +
> include/configs/T1040QDS.h | 58 +++++++++++++++---
> 7 files changed, 227 insertions(+), 11 deletions(-)
> create mode 100644 board/freescale/t1040qds/spl.c
>
> diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
> index 8f0057b..8f3d7ef 100644
> --- a/board/freescale/t1040qds/Makefile
> +++ b/board/freescale/t1040qds/Makefile
> @@ -8,9 +8,16 @@ include $(TOPDIR)/config.mk
>
> LIB = $(obj)lib$(BOARD).o
>
> +ifdef CONFIG_SPL_BUILD
> +COBJS-y += spl.o
> +endif
> +
> +ifndef CONFIG_SPL_BUILD
> COBJS-y += $(BOARD).o
> +COBJS-$(CONFIG_PCI) += pci.o
> +endif
Use "else".
> diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README
> index f8b53b4..0e4d32e 100644
> --- a/board/freescale/t1040qds/README
> +++ b/board/freescale/t1040qds/README
> @@ -167,3 +167,36 @@ T1042 Personality
> --------------------
> T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
> Ethernet switch. Rest of the blocks are same as T1040
> +
> +
> +2 Stage boot loader
> +-------------------
> +PBL initialise the internal SRAM and copy SPL(192K) in SRAM.
> +SPL further initialise DDR using SPD and environment variables and copy
> +u-boot(512 KB) from flash to DDR.
> +Finally SPL transer control to u-boot for futher booting.
> +
> +SPL has following features:
> + - Executes within 256K
> + - Actual SPL size 96K + padding till 192K for extra code
> + - No relocation required
> +
> + Run time view of SPL framework :-
> + -----------------------------------------------
> + Area | Address |
> + -----------------------------------------------
> + GD, BD | 0x0xFFFC0000 (4K) |
s/0x0x/0x/
> + -----------------------------------------------
> + HEAP | 0xFFFC1000 (40K) grow downwards |
> + -----------------------------------------------
> + STACK | 0xFFFD0000 (20K) grow upwards |
> + -----------------------------------------------
> + U-boot SPL | 0xfffD0000 - 0xfffffffc (192K) |
> + -----------------------------------------------
Usually the heap grows upwards (or more accurately these days, a
predefined area is given to malloc to allocate however it wants,
assuming you haven't substituted some simple allocator) and the stack
grows downwards (again ideally within a defined area).
I'd just remove the language about growing. It makes it ambiguous
whether the addresses you provide are the start or the end of the range.
> +Command to build 2 stage NAND boot loader
> + - modify RCW at board/freescale/t1040qds/t1040_rcw.cfg for nand boot
> + -66000002 00000000 fc027000 01000000
> + +66000002 00000000 ec106000 01000000
> + - make T1040QDS_NAND_config
> + - make u-boot-with-spl-pbl.bin
Please find some way for this RCW modification to happen automatically
as part of the build process for NAND targets.
Could you describe what is being changed in the RCW?
> diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
> index 4fd17da..dd2e0cb 100644
> --- a/board/freescale/t1040qds/ddr.c
> +++ b/board/freescale/t1040qds/ddr.c
> @@ -107,11 +107,14 @@ phys_size_t initdram(int board_type)
>
> puts("Initializing....using SPD\n");
>
> +#ifdef CONFIG_SPL_BUILD
> dram_size = fsl_ddr_sdram();
>
> dram_size = setup_ddr_tlbs(dram_size / 0x100000);
> dram_size *= 0x100000;
> -
> - puts(" DDR: ");
> +#else
> + puts("DDR has been initialised by pre loader\n");
> + dram_size = 0x80000000;
> +#endif
PBI should not be initializing DDR -- only SRAM.
> +unsigned long get_board_sys_clk(void)
> +{
> + u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
> +
> + switch (sysclk_conf & 0x0F) {
> + case QIXIS_SYSCLK_64:
> + return 64000000;
> + case QIXIS_SYSCLK_83:
> + return 83333333;
> + case QIXIS_SYSCLK_100:
> + return 100000000;
> + case QIXIS_SYSCLK_125:
> + return 125000000;
> + case QIXIS_SYSCLK_133:
> + return 133333333;
> + case QIXIS_SYSCLK_150:
> + return 150000000;
> + case QIXIS_SYSCLK_160:
> + return 160000000;
> + case QIXIS_SYSCLK_166:
> + return 166666666;
> + }
> + return 66666666;
> +}
> +
> +unsigned long get_board_ddr_clk(void)
> +{
> + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
> +
> + switch ((ddrclk_conf & 0x30) >> 4) {
> + case QIXIS_DDRCLK_100:
> + return 100000000;
> + case QIXIS_DDRCLK_125:
> + return 125000000;
> + case QIXIS_DDRCLK_133:
> + return 133333333;
> + }
> + return 66666666;
> +}
Can you factor these out into a non-SPL-specific file?
> +void board_init_f(ulong bootflag)
> +{
> + u32 plat_ratio, sys_clk, uart_clk;
> + u32 stack = CONFIG_SPL_RELOC_STACK;
> + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
> +
> + console_init_f();
> +
> + /* initialize selected port with appropriate baud rate */
> + sys_clk = get_board_sys_clk();
> + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
> + uart_clk = sys_clk * plat_ratio / 2;
> +
> + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
> + uart_clk / 16 / CONFIG_BAUDRATE);
> +
> + /* clear BSS segment */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + /* Set STACK pointer */
> + asm volatile ("lwz 1, %0" : : "m"(stack));
NACK
You cannot change the stack pointer behind the compiler's back.
> + board_init_r(NULL, 0x0);
> +}
> +
> +void board_init_r(gd_t *gd, ulong dest_addr)
> +{
> + /* Pointer is writable since we allocated a register for it */
> + gd = (gd_t *)CONFIG_SPL_GD_ADDR;
Why don't you just pass CONFIG_SPL_GD_ADDR as the argument to
board_init_r() instead of passing NULL and then setting it here?
> + bd_t *bd;
> +
> + memset(gd, 0, sizeof(gd_t));
> + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
> + memset(bd, 0, sizeof(bd_t));
> + gd->bd = bd;
> + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
> + bd->bi_memsize = CONFIG_SYS_L3_SIZE;
> +
> + probecpu();
> + get_clocks();
> + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
> + CONFIG_SPL_RELOC_MALLOC_SIZE);
> + env_init();
> +
> + /* relocate environment function pointers etc. */
> + env_relocate();
> +
> + i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
> +
> + gd->ram_size = initdram(0);
> + puts("Second program loader running in sram...\n");
The SPL was executing in SRAM from the beginning. This message is not
an appropriate way to say "I've initialized the DDR controller and done
nothing with it so far".
> +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
> + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
> + MAS3_SX|MAS3_SW|MAS3_SR, 0,
> + 0, 17, BOOKE_PAGESZ_2G, 1)
> +#endif
MAS2_M
-Scott
More information about the U-Boot
mailing list