[U-Boot] [PATCH 12/14] ARM: AM43xx: EPOS_EVM: Add support for LPDDR2

[Lokesh Vutla]

On Wednesday 06 November 2013 06:27 PM, Vaibhav Bedia wrote:
> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla <lokeshvutla at ti.com> wrote:
>> AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
>> Adding LPDDR2 init sequence and register details for the same.
>> Below is the brief description of LPDDR2 init sequence:
>> -> Configure VTP
>> -> Configure DDR IO settings
>> -> Disable initialization and refreshes until EMIF registers are programmed.
>> -> Program Timing registers
>> -> Program PHY control and Temp alert and ZQ config registers.
>> -> Enable initialization and refreshes and configure SDRAM CONFIG register
>> -> Wait till initialization is complete and the configure MR registers.
>>
> 
> Is there any public documentation to go with this?
> I would suggest sprinkling the code with comments
> to mention the different stages.
Yep ll add the comments in the code..
> 
> BTW, no IO powerdown setting for now?
You mean DDR IO settings?
> 
> [...]
>>
>> +ifeq ($(CONFIG_AM43XX),)
>> +COBJS  += ddr.o
>> +COBJS  += emif4.o
>> +endif
>> +COBJS-$(CONFIG_AM43XX) += emif4d5.o
>> +
> 
> Are the steps really different enough to warrant a new file? Can't the changes
> be handled properly in the code? How has this been handled in OMAPx where
> DDR3 and LPDDR both are supported?
Initially Tom also suggested not to use a new file. I tried with not to add a new file,
but I ended up with many #ifdefs. EMIF is new IP(reused from OMAP5) very different from AM33xx EMIF IP.
So to make things more cleaner I had to use a new file..

Thanks and regards,
Lokesh

> 
> Regards,
> Vaibhav
>