[U-Boot] [PATCH V2 1/2] driver:usb:s3c_udc: add support for Exynos4x12

[Piotr Wilczek]

Dear Jaehoon,

> -----Original Message-----
> From: Jaehoon Chung [mailto:jh80.chung at samsung.com]
> Sent: Thursday, November 07, 2013 5:49 AM
> To: Piotr Wilczek; u-boot at lists.denx.de
> Cc: Kyungmin Park
> Subject: Re: [U-Boot] [PATCH V2 1/2] driver:usb:s3c_udc: add support
> for Exynos4x12
> 
> Dear Piotr.
> 
> On 11/06/2013 10:46 PM, Piotr Wilczek wrote:
> > This patch add new defines for usb phy for Exynos4x12.
> >
> > Signed-off-by: Piotr Wilczek <p.wilczek at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > CC: Minkyu Kang <mk7.kang at samsung.com>
> > ---
> > Changes for v2:
> >  - no changes
> >
> >  drivers/usb/gadget/regs-otg.h    |    5 +++++
> >  drivers/usb/gadget/s3c_udc_otg.c |   10 ++++++++--
> >  2 files changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/usb/gadget/regs-otg.h
> > b/drivers/usb/gadget/regs-otg.h index 84bfcc5..ac5d112 100644
> > --- a/drivers/usb/gadget/regs-otg.h
> > +++ b/drivers/usb/gadget/regs-otg.h
> > @@ -226,6 +226,11 @@ struct s3c_usbotg_reg {
> >  #define CLK_SEL_12MHZ                   (0x2 << 0)
> >  #define CLK_SEL_48MHZ                   (0x0 << 0)
> >
> > +#define EXYNOS4X12_ID_PULLUP0		(0x01 << 3)
> > +#define EXYNOS4X12_COMMON_ON_N0	(0x01 << 4)
> > +#define EXYNOS4X12_CLK_SEL_12MHZ	(0x02 << 0)
> > +#define EXYNOS4X12_CLK_SEL_24MHZ	(0x05 << 0)
> > +
> >  /* Device Configuration Register DCFG */
> >  #define DEV_SPEED_HIGH_SPEED_20         (0x0 << 0)
> >  #define DEV_SPEED_FULL_SPEED_20         (0x1 << 0)
> > diff --git a/drivers/usb/gadget/s3c_udc_otg.c
> > b/drivers/usb/gadget/s3c_udc_otg.c
> > index 7e20209..cecd280 100644
> > --- a/drivers/usb/gadget/s3c_udc_otg.c
> > +++ b/drivers/usb/gadget/s3c_udc_otg.c
> > @@ -36,6 +36,7 @@
> >  #include "regs-otg.h"
> >  #include <usb/lin_gadget_compat.h>
> >
> > +
> remove white-space.
I will, thanks for review.

> 
> >  /***********************************************************/
> >
> >  #define OTG_DMA_MODE		1
> > @@ -167,8 +168,13 @@ void otg_phy_init(struct s3c_udc *dev)
> >  		writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 |
> ANALOG_PWRDOWN)
> >  			&~FORCE_SUSPEND_0), &phy->phypwr);
> >
> > -	writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
> > -	       CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
> > +	if (s5p_cpu_id == 0x4412)
> > +		writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
> > +			EXYNOS4X12_COMMON_ON_N0)) |
EXYNOS4X12_CLK_SEL_24MHZ,
> > +		       &phy->phyclk); /* PLL 24Mhz */
> > +	else
> > +		writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0))
> |
> > +		       CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
> >
> >  	writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
> >  	       | PHY_SW_RST0, &phy->rstcon);
> >

Best regards,
Piotr Wilczek