[U-Boot] [PATCH 1/4] udoo: Add Ethernet support.

[Stefano Babic]

Hi Giuseppe,

On 06/11/2013 21:33, Giuseppe Pagano wrote:
> Add Ethernet and networking support on uDoo board (FEC + phy Micrel)
> 
> 
> Signed-off-by: Giuseppe Pagano <giuseppe.pagano at seco.com>
> Cc: sbabic at denx.de
> 
> ---
> 
> diff -uNr a/board/udoo/udoo.c b/board/udoo/udoo.c
> --- a/board/udoo/udoo.c
> +++ b/board/udoo/udoo.c
> @@ -9,6 +9,7 @@
>  #include <asm/arch/clock.h>
>  #include <asm/arch/imx-regs.h>
>  #include <asm/arch/iomux.h>
> +#include <malloc.h>
>  #include <asm/arch/mx6-pins.h>
>  #include <asm/errno.h>
>  #include <asm/gpio.h>
> @@ -18,6 +19,9 @@
>  #include <asm/arch/crm_regs.h>
>  #include <asm/io.h>
>  #include <asm/arch/sys_proto.h>
> +#include <micrel.h>
> +#include <miiphy.h>
> +#include <netdev.h>
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -25,6 +29,9 @@
>         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
>         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
>  
> +#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
> +	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
>  #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
>         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
>         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
> @@ -58,6 +65,99 @@
>         MX6_PAD_EIM_D19__GPIO_3_19,
>  };
>  
> +int mx6_rgmii_rework(struct phy_device *phydev)
> +{
> +	/* To advertise only 10 Mbs */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x4, 0x61);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x9, 0x0c00);
> +

Why only 10 Mb/s ? I think the Micrel 9031 allows 1Gb/s.

Generally, use defines instead of hard coded values.

> +	/* enable master mode, force phy to 100Mbps */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x9, 0x1c00);
> +
> +	/* min rx data delay */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x0b, 0x8105);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x0c, 0x0000);
> +
> +	/* max rx/tx clock delay, min rx/tx control delay */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x0b, 0x8104);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x0c, 0xf0f0);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x0b, 0x104);
> +
> +	/* min rx data delay */
> +	ksz9021_phy_extended_write(phydev,
> +				   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);

Is is 9021 or 9031 ?

> +
> +static void setup_iomux_enet(void)
> +{
> +	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
> +	udelay(20);
> +	gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power on of enet */
> +
> +	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
> +
> +	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
> +	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
> +	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
> +	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
> +	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
> +	udelay(1000 * 10);
> +
> +	gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY rst */

SABRE as comment is maybe wrong

> +#define CONFIG_PHY_MICREL_KSZ9021

Ok, it is 9021 - please be consistent with the comments avoiding mixing
9031 and 9021.

Best regards,
Stefano Babic


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