[U-Boot] [RESEND PATCH v14 07/10] arm64: core support

[Scott Wood]

On Tue, 2013-10-15 at 11:34 +0800, fenghua at phytium.com.cn wrote:
> +/*
> + * void __asm_flush_dcache_level(level)
> + *
> + * clean and invalidate one level cache.
> + *
> + * x0: cache level
> + * x1~x9: clobbered
> + */
> +ENTRY(__asm_flush_dcache_level)
> +	lsl	x1, x0, #1
> +	msr	csselr_el1, x1		/* select cache level */
> +	isb				/* isb to sych the new cssr & csidr */
> +	mrs	x6, ccsidr_el1		/* read the new ccsidr */
> +	and	x2, x6, #7		/* x2 <- length of the cache lines */
> +	add	x2, x2, #4		/* add 4 (line length offset) */
> +	mov	x3, #0x3ff
> +	and	x3, x3, x6, lsr #3	/* x3 <- maximum number of way size */
> +	clz	w5, w3			/* bit position of way size */

You should round up (so "add w3, w3, w3; sub w3, w3, #1" before clz),
since the architecture allows non-power-of-2 values for #sets/#ways.

Also s/way size/#ways/ and s/set size/#sets/

When I see "set size" I think of the number of ways times the size of a
cache line, not the number of sets.

BTW, I see some very similar comments, register usage, and code
structure in the Linux code.  Are you *sure* this code wasn't derived
from it (or some other common source)?  Do we need to start from
scratch, if we can't trust that you're identifying all the code that you
didn't write yourself?  You were asked several times to do so.

> +loop_level:
> +	lsl	x1, x0, #1
> +	add	x1, x1, x0		/* x0 <- 3x cache level */

Comment says x0 gets "3x cache level", but the value is placed in x1.

> +	sub	x3, x2, #1
> +	bic	x0, x0, x3
> +1:      dc	civac, x0		/* clean & invalidate D/unified line */
> +	add	x0, x0, x2

Whitespace

> +	/* load TTBR0 */
> +	el = curent_el();
> +	if (el == 1)
> +		asm volatile("msr ttbr0_el1, %0"
> +			     : : "r" (gd->arch.tlb_addr) : "memory");
> +	else if (el == 2)
> +		asm volatile("msr ttbr0_el2, %0"
> +			     : : "r" (gd->arch.tlb_addr) : "memory");
> +	else
> +		panic("Not Supported Exception Level");

Do we really need to support running in either el1 or el2 at runtime,
throughout U-Boot?  If Linux is started in el2, it enters el1 after
setting up exception vectors to get control back if it needs to.  Can't
we do the same (and go back to el2 if available immediately before
entering an OS)?  Assuming we don't want to just set the expected
exception level at compile time.

-Scott