[U-Boot] [PATCH 2/5] arm: omap3: Add SPL support to tao3530

[Tapani Utriainen]

SPL works also on TAO-3530 rev Cx (using mmc and Tsunami baseboard).

Tested-by: Tapani Utriainen <tapani at technexion.com>

On Tue, 12 Nov 2013 13:15:00 +0100
Stefan Roese <sr at denx.de> wrote:

> Add SPL support for the Technexion TAO3530 SOM to replace
> x-loader. Tested with the Thunder baseboard. Currently this is
> only tested with the TAO3530 SOM revision (Ax/Bx).
> 
> Tested by booting via MMC and NAND.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Tapani Utriainen <tapani at technexion.com>
> Cc: Thorsten Eisbein <thorsten.eisbein at head-acoustics.de>
> Cc: Tom Rini <trini at ti.com>
> ---
>  board/technexion/tao3530/tao3530.c | 27 +++++++++++++++-
>  include/configs/tao3530.h          | 64 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 90 insertions(+), 1 deletion(-)
> 
> diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
> index 9482f35..7cf5aa6 100644
> --- a/board/technexion/tao3530/tao3530.c
> +++ b/board/technexion/tao3530/tao3530.c
> @@ -67,6 +67,31 @@ out:
>  	return ret;
>  }
>  
> +#ifdef CONFIG_SPL_BUILD
> +/*
> + * Routine: get_board_mem_timings
> + * Description: If we use SPL then there is no x-loader nor config header
> + * so we have to setup the DDR timings ourself on both banks.
> + */
> +void get_board_mem_timings(struct board_sdrc_timings *timings)
> +{
> +	if (tao3530_revision() < 3) {
> +		/* 256MB / Bank */
> +		timings->mcfg = MCFG(256 << 20, 14);	/* RAS-width 14 */
> +		timings->ctrla = HYNIX_V_ACTIMA_165;
> +		timings->ctrlb = HYNIX_V_ACTIMB_165;
> +	} else {
> +		/* 128MB / Bank */
> +		timings->mcfg = MCFG(128 << 20, 13);	/* RAS-width 13 */
> +		timings->ctrla = MICRON_V_ACTIMA_165;
> +		timings->ctrlb = MICRON_V_ACTIMB_165;
> +	}
> +
> +	timings->mr = MICRON_V_MR_165;
> +	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +}
> +#endif
> +
>  /*
>   * Routine: board_init
>   * Description: Early hardware init.
> @@ -134,7 +159,7 @@ void set_muxconf_regs(void)
>  	MUX_TAO3530();
>  }
>  
> -#ifdef CONFIG_GENERIC_MMC
> +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
>  int board_mmc_init(bd_t *bis)
>  {
>  	omap_mmc_init(0, 0, 0, -1, -1);
> diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
> index 6327161..03eb85e 100644
> --- a/include/configs/tao3530.h
> +++ b/include/configs/tao3530.h
> @@ -5,6 +5,8 @@
>   * Edward Lin <linuxfae at technexion.com>
>   * Tapani Utriainen <linuxfae at technexion.com>
>   *
> + * Copyright (C) 2013 Stefan Roese <sr at denx.de>
> + *
>   * SPDX-License-Identifier:	GPL-2.0+
>   */
>  
> @@ -307,4 +309,66 @@
>  #define CONFIG_USB_STORAGE
>  #define CONGIG_CMD_STORAGE
>  
> +/* Defines for SPL */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_NAND_SIMPLE
> +
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
> +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
> +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
> +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
> +
> +#define CONFIG_SPL_BOARD_INIT
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBDISK_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_FAT_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_NAND_BASE
> +#define CONFIG_SPL_NAND_DRIVERS
> +#define CONFIG_SPL_NAND_ECC
> +#define CONFIG_SPL_GPIO_SUPPORT
> +#define CONFIG_SPL_POWER_SUPPORT
> +#define CONFIG_SPL_OMAP3_ID_NAND
> +#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
> +
> +/* NAND boot config */
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_PAGE_COUNT	64
> +#define CONFIG_SYS_NAND_PAGE_SIZE	2048
> +#define CONFIG_SYS_NAND_OOBSIZE		64
> +#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
> +/*
> + * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
> + * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
> + */
> +#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
> +					 10, 11, 12, 13 }
> +#define CONFIG_SYS_NAND_ECCSIZE		512
> +#define CONFIG_SYS_NAND_ECCBYTES	3
> +
> +#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
> +
> +#define CONFIG_SPL_TEXT_BASE		0x40200800
> +#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
> +#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
> +
> +/*
> + * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
> + * older x-loader implementations. And move the BSS area so that it
> + * doesn't overlap with TEXT_BASE.
> + */
> +#define CONFIG_SYS_TEXT_BASE		0x80008000
> +#define CONFIG_SPL_BSS_START_ADDR	0x80100000
> +#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
> +
> +#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
> +
>  #endif /* __CONFIG_H */