[U-Boot] i2c issues with efikamx and mainline uboot

Marek Vasut marex at denx.de
Tue Nov 19 16:37:00 CET 2013


Dear Konstantinos Margaritis,

> (Disclaimer: u-boot newbie)
> 
> Hi all,
> 
> With Marek's huge help (thanks Marek!) I've tried to merge his tree [1]
> that provides lcd support for the efikamx/efikasb with recent mainline
> uboot. It boots, but I've hit some wall now and couldn't get passed it,
> so I thought I'd ask for some expert advice, Marek suggested I mail
> here and CC himself and Stefano as well.
> 
> So, I've migrated the structures to the iomux v3 coding conventions,
> added some missing defines for iomuxes used, etc. I've forked the code
> in github [2] and am doing all the changes there, in the hope that I can
> at some point submit it back to mainline. I also want to to enable
> multi-host USB support for the platform so that tftp booting will be at
> last possible, but that's going to happen later, I want to be done with
> LCD first.
> 
> The result boots, but in short it fails to initialise the LCD (for the
> efikamx, didn't test efikasb yet). I noticed that amongst many changes,
> in drivers/i2c/mxc_i2c.c, i2c_imx_bus_busy() in Marek's tree () got
> sort of replaced with wait_for_sr_state(), which does the same
> thing but is more generic -or so I understand, please correct me if I'm
> wrong in my interpretation.
> 
> So what's the problem? Well, I2CR_MSTA (master mode) is set, but
> I2SR_IBB fails to get set. In every case I get this result in the
> I2SR register:
> 
> I2SR = 81 -> I2SR_ICF | I2SR_RX_NO_AK, ie.
> 
> which according to the iMX515 Reference Manual corresponds to:
> 
> "Transfer is complete, and set by the falling edge of the ninth clock
> of a byte transfer." + "A “No acknowledge” signal was detected
> at the ninth clock."
> 
> so a previous answer didn't send an acknowledge or rather the
> opposite it sent a NACK.
> 
> I'm at a loss here, attaching a boot log where I added some printfs
> around. I'd appreciate any pointer as to what I'm doing wrong.

Honestly, I have a feeling the MX51 I2C controller might be broken. Isn't there 
maybe something in the ERRATA for MX51 (I know it's HUGE) ?

Best regards,
Marek Vasut


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