[U-Boot] [PATCH 7/9] ARM: HYP/non-sec: add the option for a second-stage monitor

[Marc Zyngier]

Allow the switch to a second stage secure monitor just before
switching to non-secure.

This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/cpu/armv7/nonsec_virt.S | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index c5a8347..f07e3f7 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -35,6 +35,12 @@ _monitor_vectors:
  * We use only r0 and r1 here, due to constraints in the caller.
  */
 _secure_monitor:
+#ifdef CONFIG_ARMV7_PSCI_BASE
+	ldr	r1, =CONFIG_ARMV7_PSCI_BASE	@ Switch to the next monitor
+	mcr	p15, 0, r1, c12, c0, 1
+	isb
+#endif
+	
 	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
 	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits
 	orr	r1, r1, #0x31			@ enable NS, AW, FW bits
@@ -50,7 +56,7 @@ _secure_monitor:
 	isb
 
 #ifdef CONFIG_ARMV7_VIRT
-	mrceq	p15, 0, r0, c12, c0, 1		@ get MVBAR value
+	adreq	r0, _monitor_vectors
 	mcreq	p15, 4, r0, c12, c0, 0		@ write HVBAR
 #endif
 	bne	1f
-- 
1.8.2.3