[U-Boot] [PATCH RFC 3/7] MIPS: AR934x: Register Bitfields for SoC ar934x
Nikolaos Pasaloukos
Nikolaos.Pasaloukos at imgtec.com
Fri Nov 29 10:48:04 CET 2013
Some bitfield declarations for ar934x registers
Signed-off-by: Nikolaos Pasaloukos <Nikolaos.Pasaloukos at imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>
---
arch/mips/include/asm/ar934x_reg_cfg.h | 1527 ++++++++++++++++++++++++++++++++
1 file changed, 1527 insertions(+)
create mode 100644 arch/mips/include/asm/ar934x_reg_cfg.h
diff --git a/arch/mips/include/asm/ar934x_reg_cfg.h b/arch/mips/include/asm/ar934x_reg_cfg.h
new file mode 100644
index 0000000..7e5d0cc
--- /dev/null
+++ b/arch/mips/include/asm/ar934x_reg_cfg.h
@@ -0,0 +1,1527 @@
+/*
+ * Atheros AR924X series processor SOC registers
+ *
+ * Copyright (C) 2008 Atheros Communications, Inc.
+ *
+ * Copyright (C) 2013 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _AR934X_SOC_H
+#define _AR934X_SOC_H
+
+/* 32'h18000000 (DDR_CONFIG) */
+#define DDR_CONFIG_CAS_LATENCY_MSB_MSB 31
+#define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31
+#define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000
+#define DDR_CONFIG_CAS_LATENCY_MSB_GET(x) \
+ (((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> \
+ DDR_CONFIG_CAS_LATENCY_MSB_LSB)
+#define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) \
+ (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & \
+ DDR_CONFIG_CAS_LATENCY_MSB_MASK)
+#define DDR_CONFIG_OPEN_PAGE_MSB 30
+#define DDR_CONFIG_OPEN_PAGE_LSB 30
+#define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000
+#define DDR_CONFIG_OPEN_PAGE_GET(x) \
+ (((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB)
+#define DDR_CONFIG_OPEN_PAGE_SET(x) \
+ (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK)
+#define DDR_CONFIG_CAS_LATENCY_MSB 29
+#define DDR_CONFIG_CAS_LATENCY_LSB 27
+#define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000
+#define DDR_CONFIG_CAS_LATENCY_GET(x) \
+ (((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB)
+#define DDR_CONFIG_CAS_LATENCY_SET(x) \
+ (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK)
+#define DDR_CONFIG_TMRD_MSB 26
+#define DDR_CONFIG_TMRD_LSB 23
+#define DDR_CONFIG_TMRD_MASK 0x07800000
+#define DDR_CONFIG_TMRD_GET(x) \
+ (((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB)
+#define DDR_CONFIG_TMRD_SET(x) \
+ (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK)
+#define DDR_CONFIG_TRFC_MSB 22
+#define DDR_CONFIG_TRFC_LSB 17
+#define DDR_CONFIG_TRFC_MASK 0x007e0000
+#define DDR_CONFIG_TRFC_GET(x) \
+ (((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB)
+#define DDR_CONFIG_TRFC_SET(x) \
+ (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK)
+#define DDR_CONFIG_TRRD_MSB 16
+#define DDR_CONFIG_TRRD_LSB 13
+#define DDR_CONFIG_TRRD_MASK 0x0001e000
+#define DDR_CONFIG_TRRD_GET(x) \
+ (((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB)
+#define DDR_CONFIG_TRRD_SET(x) \
+ (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK)
+#define DDR_CONFIG_TRP_MSB 12
+#define DDR_CONFIG_TRP_LSB 9
+#define DDR_CONFIG_TRP_MASK 0x00001e00
+#define DDR_CONFIG_TRP_GET(x) \
+ (((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB)
+#define DDR_CONFIG_TRP_SET(x) \
+ (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK)
+#define DDR_CONFIG_TRCD_MSB 8
+#define DDR_CONFIG_TRCD_LSB 5
+#define DDR_CONFIG_TRCD_MASK 0x000001e0
+#define DDR_CONFIG_TRCD_GET(x) \
+ (((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB)
+#define DDR_CONFIG_TRCD_SET(x) \
+ (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK)
+#define DDR_CONFIG_TRAS_MSB 4
+#define DDR_CONFIG_TRAS_LSB 0
+#define DDR_CONFIG_TRAS_MASK 0x0000001f
+#define DDR_CONFIG_TRAS_GET(x) \
+ (((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB)
+#define DDR_CONFIG_TRAS_SET(x) \
+ (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
+#define DDR_CONFIG_ADDRESS 0x18000000
+
+/* 32'h18000004 (DDR_CONFIG2) */
+#define DDR_CONFIG2_HALF_WIDTH_LOW_MSB 31
+#define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31
+#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000
+#define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x) \
+ (((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> \
+ DDR_CONFIG2_HALF_WIDTH_LOW_LSB)
+#define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) \
+ (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & \
+ DDR_CONFIG2_HALF_WIDTH_LOW_MASK)
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB 29
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x) \
+ (((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> \
+ DDR_CONFIG2_GATE_OPEN_LATENCY_LSB)
+#define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) \
+ (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & \
+ DDR_CONFIG2_GATE_OPEN_LATENCY_MASK)
+#define DDR_CONFIG2_TWTR_MSB 25
+#define DDR_CONFIG2_TWTR_LSB 21
+#define DDR_CONFIG2_TWTR_MASK 0x03e00000
+#define DDR_CONFIG2_TWTR_GET(x) \
+ (((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB)
+#define DDR_CONFIG2_TWTR_SET(x) \
+ (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK)
+#define DDR_CONFIG2_TRTP_MSB 20
+#define DDR_CONFIG2_TRTP_LSB 17
+#define DDR_CONFIG2_TRTP_MASK 0x001e0000
+#define DDR_CONFIG2_TRTP_GET(x) \
+ (((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB)
+#define DDR_CONFIG2_TRTP_SET(x) \
+ (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK)
+#define DDR_CONFIG2_TRTW_MSB 16
+#define DDR_CONFIG2_TRTW_LSB 12
+#define DDR_CONFIG2_TRTW_MASK 0x0001f000
+#define DDR_CONFIG2_TRTW_GET(x) \
+ (((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB)
+#define DDR_CONFIG2_TRTW_SET(x) \
+ (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK)
+#define DDR_CONFIG2_TWR_MSB 11
+#define DDR_CONFIG2_TWR_LSB 8
+#define DDR_CONFIG2_TWR_MASK 0x00000f00
+#define DDR_CONFIG2_TWR_GET(x) \
+ (((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB)
+#define DDR_CONFIG2_TWR_SET(x) \
+ (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK)
+#define DDR_CONFIG2_CKE_MSB 7
+#define DDR_CONFIG2_CKE_LSB 7
+#define DDR_CONFIG2_CKE_MASK 0x00000080
+#define DDR_CONFIG2_CKE_GET(x) \
+ (((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB)
+#define DDR_CONFIG2_CKE_SET(x) \
+ (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK)
+#define DDR_CONFIG2_PHASE_SELECT_MSB 6
+#define DDR_CONFIG2_PHASE_SELECT_LSB 6
+#define DDR_CONFIG2_PHASE_SELECT_MASK 0x00000040
+#define DDR_CONFIG2_PHASE_SELECT_GET(x) \
+ (((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB)
+#define DDR_CONFIG2_PHASE_SELECT_SET(x) \
+ (((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK)
+#define DDR_CONFIG2_CNTL_OE_EN_MSB 5
+#define DDR_CONFIG2_CNTL_OE_EN_LSB 5
+#define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020
+#define DDR_CONFIG2_CNTL_OE_EN_GET(x) \
+ (((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB)
+#define DDR_CONFIG2_CNTL_OE_EN_SET(x) \
+ (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK)
+#define DDR_CONFIG2_BURST_TYPE_MSB 4
+#define DDR_CONFIG2_BURST_TYPE_LSB 4
+#define DDR_CONFIG2_BURST_TYPE_MASK 0x00000010
+#define DDR_CONFIG2_BURST_TYPE_GET(x) \
+ (((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB)
+#define DDR_CONFIG2_BURST_TYPE_SET(x) \
+ (((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK)
+#define DDR_CONFIG2_BURST_LENGTH_MSB 3
+#define DDR_CONFIG2_BURST_LENGTH_LSB 0
+#define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f
+#define DDR_CONFIG2_BURST_LENGTH_GET(x) \
+ (((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB)
+#define DDR_CONFIG2_BURST_LENGTH_SET(x) \
+ (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK)
+#define DDR_CONFIG2_ADDRESS 0x18000004
+
+/* 32'h180000b8 (DDR_DDR2_CONFIG) */
+#define DDR2_CONFIG_DDR2_TWL_MSB 13
+#define DDR2_CONFIG_DDR2_TWL_LSB 10
+#define DDR2_CONFIG_DDR2_TWL_MASK 0x00003c00
+#define DDR2_CONFIG_DDR2_TWL_GET(x) \
+ (((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB)
+#define DDR2_CONFIG_DDR2_TWL_SET(x) \
+ (((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK)
+#define DDR2_CONFIG_DDR2_ODT_MSB 9
+#define DDR2_CONFIG_DDR2_ODT_LSB 9
+#define DDR2_CONFIG_DDR2_ODT_MASK 0x00000200
+#define DDR2_CONFIG_DDR2_ODT_GET(x) \
+ (((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB)
+#define DDR2_CONFIG_DDR2_ODT_SET(x) \
+ (((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK)
+#define DDR2_CONFIG_TFAW_MSB 7
+#define DDR2_CONFIG_TFAW_LSB 2
+#define DDR2_CONFIG_TFAW_MASK 0x000000fc
+#define DDR2_CONFIG_TFAW_GET(x) \
+ (((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB)
+#define DDR2_CONFIG_TFAW_SET(x) \
+ (((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK)
+#define DDR2_CONFIG_ENABLE_DDR2_MSB 0
+#define DDR2_CONFIG_ENABLE_DDR2_LSB 0
+#define DDR2_CONFIG_ENABLE_DDR2_MASK 0x00000001
+#define DDR2_CONFIG_ENABLE_DDR2_GET(x) \
+ (((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB)
+#define DDR2_CONFIG_ENABLE_DDR2_SET(x) \
+ (((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK)
+
+/* 32'h18000108 (DDR_CTL_CONFIG) */
+#define DDR_CTL_CONFIG_SRAM_TSEL_MSB 31
+#define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30
+#define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000
+#define DDR_CTL_CONFIG_SRAM_TSEL_GET(x) \
+ (((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB)
+#define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) \
+ (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK)
+#define DDR_CTL_CONFIG_SRAM_TSEL_RESET 0x1
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) \
+ (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> \
+ DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB)
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) \
+ (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & \
+ DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK)
+#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET 0x0
+#define DDR_CTL_CONFIG_SPARE_MSB 20
+#define DDR_CTL_CONFIG_SPARE_LSB 7
+#define DDR_CTL_CONFIG_SPARE_MASK 0x001fff80
+#define DDR_CTL_CONFIG_SPARE_GET(x) \
+ (((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB)
+#define DDR_CTL_CONFIG_SPARE_SET(x) \
+ (((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK)
+#define DDR_CTL_CONFIG_SPARE_RESET 0x2
+#define DDR_CTL_CONFIG_DDR2_EN_MSB 6
+#define DDR_CTL_CONFIG_DDR2_EN_LSB 6
+#define DDR_CTL_CONFIG_DDR2_EN_MASK 0x00000040
+#define DDR_CTL_CONFIG_DDR2_EN_GET(x) \
+ (((x) & DDR_CTL_CONFIG_DDR2_EN_MASK) >> DDR_CTL_CONFIG_DDR2_EN_LSB)
+#define DDR_CTL_CONFIG_DDR2_EN_SET(x) \
+ (((x) << DDR_CTL_CONFIG_DDR2_EN_LSB) & DDR_CTL_CONFIG_DDR2_EN_MASK)
+#define DDR_CTL_CONFIG_DDR2_EN_RESET 0x0
+#define DDR_CTL_CONFIG_PREFETCH_CNT_MSB 5
+#define DDR_CTL_CONFIG_PREFETCH_CNT_LSB 2
+#define DDR_CTL_CONFIG_PREFETCH_CNT_MASK 0x0000003c
+#define DDR_CTL_CONFIG_PREFETCH_CNT_GET(x) \
+ (((x) & DDR_CTL_CONFIG_PREFETCH_CNT_MASK) >> \
+ DDR_CTL_CONFIG_PREFETCH_CNT_LSB)
+#define DDR_CTL_CONFIG_PREFETCH_CNT_SET(x) \
+ (((x) << DDR_CTL_CONFIG_PREFETCH_CNT_LSB) & \
+ DDR_CTL_CONFIG_PREFETCH_CNT_MASK)
+#define DDR_CTL_CONFIG_PREFETCH_CNT_RESET 0x3
+#define DDR_CTL_CONFIG_HALF_WIDTH_MSB 1
+#define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1
+#define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002
+#define DDR_CTL_CONFIG_HALF_WIDTH_GET(x) \
+ (((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> \
+ DDR_CTL_CONFIG_HALF_WIDTH_LSB)
+#define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) \
+ (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & \
+ DDR_CTL_CONFIG_HALF_WIDTH_MASK)
+#define DDR_CTL_CONFIG_HALF_WIDTH_RESET 0x1
+#define DDR_CTL_CONFIG_SRAM_MODE_EN_MSB 0
+#define DDR_CTL_CONFIG_SRAM_MODE_EN_LSB 0
+#define DDR_CTL_CONFIG_SRAM_MODE_EN_MASK 0x00000001
+#define DDR_CTL_CONFIG_SRAM_MODE_EN_GET(x) \
+ (((x) & DDR_CTL_CONFIG_SRAM_MODE_EN_MASK) >> \
+ DDR_CTL_CONFIG_SRAM_MODE_EN_LSB)
+#define DDR_CTL_CONFIG_SRAM_MODE_EN_SET(x) \
+ (((x) << DDR_CTL_CONFIG_SRAM_MODE_EN_LSB) & \
+ DDR_CTL_CONFIG_SRAM_MODE_EN_MASK)
+#define DDR_CTL_CONFIG_SRAM_MODE_EN_RESET 0x0
+#define DDR_CTL_CONFIG_ADDRESS 0x18000108
+
+/* 32'h18040030 (GPIO_OUT_FUNCTION1) */
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) \
+ (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> \
+ GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) \
+ (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & \
+ GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xb
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) \
+ (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> \
+ GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) \
+ (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & \
+ GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0xa
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) \
+ (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> \
+ GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) \
+ (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & \
+ GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) \
+ (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> \
+ GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) \
+ (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & \
+ GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK)
+#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x14
+#define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030
+
+#define GPIO_INPUT_ENABLE_BIT(x) (1 << (x))
+
+/* 32'h18050000 (CPU_PLL_CONFIG) */
+#define CPU_PLL_CONFIG_UPDATING_MSB 31
+#define CPU_PLL_CONFIG_UPDATING_LSB 31
+#define CPU_PLL_CONFIG_UPDATING_MASK 0x80000000
+#define CPU_PLL_CONFIG_UPDATING_GET(x) \
+ (((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB)
+#define CPU_PLL_CONFIG_UPDATING_SET(x) \
+ (((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK)
+#define CPU_PLL_CONFIG_UPDATING_RESET 1
+#define CPU_PLL_CONFIG_PLLPWD_MSB 30
+#define CPU_PLL_CONFIG_PLLPWD_LSB 30
+#define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
+#define CPU_PLL_CONFIG_PLLPWD_GET(x) \
+ (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB)
+#define CPU_PLL_CONFIG_PLLPWD_SET(x) \
+ (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
+#define CPU_PLL_CONFIG_PLLPWD_RESET 1
+#define CPU_PLL_CONFIG_SPARE_MSB 29
+#define CPU_PLL_CONFIG_SPARE_LSB 22
+#define CPU_PLL_CONFIG_SPARE_MASK 0x3fc00000
+#define CPU_PLL_CONFIG_SPARE_GET(x) \
+ (((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB)
+#define CPU_PLL_CONFIG_SPARE_SET(x) \
+ (((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK)
+#define CPU_PLL_CONFIG_SPARE_RESET 0
+#define CPU_PLL_CONFIG_OUTDIV_MSB 21
+#define CPU_PLL_CONFIG_OUTDIV_LSB 19
+#define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000
+#define CPU_PLL_CONFIG_OUTDIV_GET(x) \
+ (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB)
+#define CPU_PLL_CONFIG_OUTDIV_SET(x) \
+ (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
+#define CPU_PLL_CONFIG_OUTDIV_RESET 0
+#define CPU_PLL_CONFIG_RANGE_MSB 18
+#define CPU_PLL_CONFIG_RANGE_LSB 17
+#define CPU_PLL_CONFIG_RANGE_MASK 0x00060000
+#define CPU_PLL_CONFIG_RANGE_GET(x) \
+ (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB)
+#define CPU_PLL_CONFIG_RANGE_SET(x) \
+ (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
+#define CPU_PLL_CONFIG_RANGE_RESET 3
+#define CPU_PLL_CONFIG_REFDIV_MSB 16
+#define CPU_PLL_CONFIG_REFDIV_LSB 12
+#define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000
+#define CPU_PLL_CONFIG_REFDIV_GET(x) \
+ (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB)
+#define CPU_PLL_CONFIG_REFDIV_SET(x) \
+ (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
+#define CPU_PLL_CONFIG_REFDIV_RESET 2
+#define CPU_PLL_CONFIG_NINT_MSB 11
+#define CPU_PLL_CONFIG_NINT_LSB 6
+#define CPU_PLL_CONFIG_NINT_MASK 0x00000fc0
+#define CPU_PLL_CONFIG_NINT_GET(x) \
+ (((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB)
+#define CPU_PLL_CONFIG_NINT_SET(x) \
+ (((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK)
+#define CPU_PLL_CONFIG_NINT_RESET 20
+#define CPU_PLL_CONFIG_NFRAC_MSB 5
+#define CPU_PLL_CONFIG_NFRAC_LSB 0
+#define CPU_PLL_CONFIG_NFRAC_MASK 0x0000003f
+#define CPU_PLL_CONFIG_NFRAC_GET(x) \
+ (((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB)
+#define CPU_PLL_CONFIG_NFRAC_SET(x) \
+ (((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK)
+#define CPU_PLL_CONFIG_NFRAC_RESET 16
+#define CPU_PLL_CONFIG_ADDRESS 0x0000
+#define CPU_PLL_CONFIG_OFFSET 0x0000
+/* SW modifiable bits */
+#define CPU_PLL_CONFIG_SW_MASK 0xffffffff
+/* bits defined at reset */
+#define CPU_PLL_CONFIG_RSTMASK 0xffffffff
+/* reset value (ignore bits undefined at reset) */
+#define CPU_PLL_CONFIG_RESET 0xc0062510
+
+/* 32'h18050004 (DDR_PLL_CONFIG) */
+#define DDR_PLL_CONFIG_UPDATING_MSB 31
+#define DDR_PLL_CONFIG_UPDATING_LSB 31
+#define DDR_PLL_CONFIG_UPDATING_MASK 0x80000000
+#define DDR_PLL_CONFIG_UPDATING_GET(x) \
+ (((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB)
+#define DDR_PLL_CONFIG_UPDATING_SET(x) \
+ (((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK)
+#define DDR_PLL_CONFIG_UPDATING_RESET 1
+#define DDR_PLL_CONFIG_PLLPWD_MSB 30
+#define DDR_PLL_CONFIG_PLLPWD_LSB 30
+#define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
+#define DDR_PLL_CONFIG_PLLPWD_GET(x) \
+ (((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB)
+#define DDR_PLL_CONFIG_PLLPWD_SET(x) \
+ (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
+#define DDR_PLL_CONFIG_PLLPWD_RESET 1
+#define DDR_PLL_CONFIG_SPARE_MSB 29
+#define DDR_PLL_CONFIG_SPARE_LSB 26
+#define DDR_PLL_CONFIG_SPARE_MASK 0x3c000000
+#define DDR_PLL_CONFIG_SPARE_GET(x) \
+ (((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB)
+#define DDR_PLL_CONFIG_SPARE_SET(x) \
+ (((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK)
+#define DDR_PLL_CONFIG_SPARE_RESET 0
+#define DDR_PLL_CONFIG_OUTDIV_MSB 25
+#define DDR_PLL_CONFIG_OUTDIV_LSB 23
+#define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000
+#define DDR_PLL_CONFIG_OUTDIV_GET(x) \
+ (((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB)
+#define DDR_PLL_CONFIG_OUTDIV_SET(x) \
+ (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
+#define DDR_PLL_CONFIG_OUTDIV_RESET 0
+#define DDR_PLL_CONFIG_RANGE_MSB 22
+#define DDR_PLL_CONFIG_RANGE_LSB 21
+#define DDR_PLL_CONFIG_RANGE_MASK 0x00600000
+#define DDR_PLL_CONFIG_RANGE_GET(x) \
+ (((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB)
+#define DDR_PLL_CONFIG_RANGE_SET(x) \
+ (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
+#define DDR_PLL_CONFIG_RANGE_RESET 3
+#define DDR_PLL_CONFIG_REFDIV_MSB 20
+#define DDR_PLL_CONFIG_REFDIV_LSB 16
+#define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000
+#define DDR_PLL_CONFIG_REFDIV_GET(x) \
+ (((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB)
+#define DDR_PLL_CONFIG_REFDIV_SET(x) \
+ (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
+#define DDR_PLL_CONFIG_REFDIV_RESET 2
+#define DDR_PLL_CONFIG_NINT_MSB 15
+#define DDR_PLL_CONFIG_NINT_LSB 10
+#define DDR_PLL_CONFIG_NINT_MASK 0x0000fc00
+#define DDR_PLL_CONFIG_NINT_GET(x) \
+ (((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB)
+#define DDR_PLL_CONFIG_NINT_SET(x) \
+ (((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK)
+#define DDR_PLL_CONFIG_NINT_RESET 20
+#define DDR_PLL_CONFIG_NFRAC_MSB 9
+#define DDR_PLL_CONFIG_NFRAC_LSB 0
+#define DDR_PLL_CONFIG_NFRAC_MASK 0x000003ff
+#define DDR_PLL_CONFIG_NFRAC_GET(x) \
+ (((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB)
+#define DDR_PLL_CONFIG_NFRAC_SET(x) \
+ (((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK)
+#define DDR_PLL_CONFIG_NFRAC_RESET 512
+#define DDR_PLL_CONFIG_ADDRESS 0x0004
+#define DDR_PLL_CONFIG_OFFSET 0x0004
+/* SW modifiable bits */
+#define DDR_PLL_CONFIG_SW_MASK 0xffffffff
+/* bits defined at reset */
+#define DDR_PLL_CONFIG_RSTMASK 0xffffffff
+/* reset value (ignore bits undefined at reset) */
+#define DDR_PLL_CONFIG_RESET 0xc0625200
+
+/* 32'h18050008 (CPU_DDR_CLOCK_CONTROL) */
+#define CPU_DDR_CLOCK_CONTROL_SPARE_MSB 31
+#define CPU_DDR_CLOCK_CONTROL_SPARE_LSB 25
+#define CPU_DDR_CLOCK_CONTROL_SPARE_MASK 0xfe000000
+#define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_SPARE_LSB)
+#define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_SPARE_MASK)
+#define CPU_DDR_CLOCK_CONTROL_SPARE_RESET 0
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB 24
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB)
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
+#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 1
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MSB 21
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB 21
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK 0x00200000
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB)
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK)
+#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_RESET 1
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MSB 20
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB 20
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK 0x00100000
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_RESET 1
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB)
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
+#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB)
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 1
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB)
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 1
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 1
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB)
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK)
+#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) \
+ (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> \
+ CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB)
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & \
+ CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK)
+#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0
+#define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x0008
+#define CPU_DDR_CLOCK_CONTROL_OFFSET 0x0008
+/* SW modifiable bits */
+#define CPU_DDR_CLOCK_CONTROL_SW_MASK 0xffffffff
+/* bits defined at reset */
+#define CPU_DDR_CLOCK_CONTROL_RSTMASK 0xffffffff
+/* reset value (ignore bits undefined at reset) */
+#define CPU_DDR_CLOCK_CONTROL_RESET 0x0130001c
+
+/* 32'h18050024 (SWITCH_CLOCK_SPARE) */
+#define SWITCH_CLOCK_SPARE_SPARE_MSB 31
+#define SWITCH_CLOCK_SPARE_SPARE_LSB 12
+#define SWITCH_CLOCK_SPARE_SPARE_MASK 0xfffff000
+#define SWITCH_CLOCK_SPARE_SPARE_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB)
+#define SWITCH_CLOCK_SPARE_SPARE_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK)
+#define SWITCH_CLOCK_SPARE_SPARE_RESET 0
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> \
+ SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB)
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & \
+ SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)
+#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 5
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> \
+ SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB)
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & \
+ SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK)
+#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MSB 6
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB 6
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK 0x00000040
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) >> \
+ SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB)
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) & \
+ SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK)
+#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_RESET 0
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MSB 5
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB 5
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK 0x00000020
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) >> \
+ SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB)
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) & \
+ SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK)
+#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_RESET 1
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MSB 4
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB 4
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK 0x00000010
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) >> \
+ SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB)
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) & \
+ SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK)
+#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_RESET 1
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MSB 3
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB 3
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK 0x00000008
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) >> \
+ SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB)
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) & \
+ SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK)
+#define SWITCH_CLOCK_SPARE_EEE_ENABLE_RESET 0
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MSB 2
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB 2
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK 0x00000004
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) >> \
+ SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB)
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) & \
+ SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK)
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_RESET 0
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MSB 1
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB 1
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK 0x00000002
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) >> \
+ SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB)
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) & \
+ SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK)
+#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_RESET 0
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MSB 0
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB 0
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK 0x00000001
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_GET(x) \
+ (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) >> \
+ SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB)
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET(x) \
+ (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) & \
+ SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK)
+#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_RESET 1
+#define SWITCH_CLOCK_SPARE_ADDRESS 0x0024
+#define SWITCH_CLOCK_SPARE_OFFSET 0x0024
+/* SW modifiable bits */
+#define SWITCH_CLOCK_SPARE_SW_MASK 0xffffffff
+/* bits defined at reset */
+#define SWITCH_CLOCK_SPARE_RSTMASK 0xffffffff
+/* reset value (ignore bits undefined at reset) */
+#define SWITCH_CLOCK_SPARE_RESET 0x00000531
+
+/* 32'h18050044 (DDR_PLL_DITHER)*/
+#define DDR_PLL_DITHER_DITHER_EN_MSB 31
+#define DDR_PLL_DITHER_DITHER_EN_LSB 31
+#define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000
+#define DDR_PLL_DITHER_DITHER_EN_GET(x) \
+ (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB)
+#define DDR_PLL_DITHER_DITHER_EN_SET(x) \
+ (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK)
+#define DDR_PLL_DITHER_DITHER_EN_RESET 0
+#define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30
+#define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27
+#define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000
+#define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) \
+ (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> \
+ DDR_PLL_DITHER_UPDATE_COUNT_LSB)
+#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) \
+ (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & \
+ DDR_PLL_DITHER_UPDATE_COUNT_MASK)
+#define DDR_PLL_DITHER_UPDATE_COUNT_RESET 15
+#define DDR_PLL_DITHER_NFRAC_STEP_MSB 26
+#define DDR_PLL_DITHER_NFRAC_STEP_LSB 20
+#define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000
+#define DDR_PLL_DITHER_NFRAC_STEP_GET(x) \
+ (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> \
+ DDR_PLL_DITHER_NFRAC_STEP_LSB)
+#define DDR_PLL_DITHER_NFRAC_STEP_SET(x) \
+ (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & \
+ DDR_PLL_DITHER_NFRAC_STEP_MASK)
+#define DDR_PLL_DITHER_NFRAC_STEP_RESET 1
+#define DDR_PLL_DITHER_NFRAC_MIN_MSB 19
+#define DDR_PLL_DITHER_NFRAC_MIN_LSB 10
+#define DDR_PLL_DITHER_NFRAC_MIN_MASK 0x000ffc00
+#define DDR_PLL_DITHER_NFRAC_MIN_GET(x) \
+ (((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB)
+#define DDR_PLL_DITHER_NFRAC_MIN_SET(x) \
+ (((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK)
+#define DDR_PLL_DITHER_NFRAC_MIN_RESET 25
+#define DDR_PLL_DITHER_NFRAC_MAX_MSB 9
+#define DDR_PLL_DITHER_NFRAC_MAX_LSB 0
+#define DDR_PLL_DITHER_NFRAC_MAX_MASK 0x000003ff
+#define DDR_PLL_DITHER_NFRAC_MAX_GET(x) \
+ (((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB)
+#define DDR_PLL_DITHER_NFRAC_MAX_SET(x) \
+ (((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK)
+#define DDR_PLL_DITHER_NFRAC_MAX_RESET 1000
+#define DDR_PLL_DITHER_ADDRESS 0x0044
+#define DDR_PLL_DITHER_OFFSET 0x0044
+/* SW modifiable bits */
+#define DDR_PLL_DITHER_SW_MASK 0xffffffff
+/* bits defined at reset */
+#define DDR_PLL_DITHER_RSTMASK 0xffffffff
+/* reset value (ignore bits undefined at reset) */
+#define DDR_PLL_DITHER_RESET 0x781067e8
+
+/* 32'h18050048 (CPU_PLL_DITHER) */
+#define CPU_PLL_DITHER_DITHER_EN_MSB 31
+#define CPU_PLL_DITHER_DITHER_EN_LSB 31
+#define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000
+#define CPU_PLL_DITHER_DITHER_EN_GET(x) \
+ (((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB)
+#define CPU_PLL_DITHER_DITHER_EN_SET(x) \
+ (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK)
+#define CPU_PLL_DITHER_DITHER_EN_RESET 0
+#define CPU_PLL_DITHER_UPDATE_COUNT_MSB 23
+#define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18
+#define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000
+#define CPU_PLL_DITHER_UPDATE_COUNT_GET(x) \
+ (((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> \
+ CPU_PLL_DITHER_UPDATE_COUNT_LSB)
+#define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) \
+ (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & \
+ CPU_PLL_DITHER_UPDATE_COUNT_MASK)
+#define CPU_PLL_DITHER_UPDATE_COUNT_RESET 20
+#define CPU_PLL_DITHER_NFRAC_STEP_MSB 17
+#define CPU_PLL_DITHER_NFRAC_STEP_LSB 12
+#define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000
+#define CPU_PLL_DITHER_NFRAC_STEP_GET(x) \
+ (((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> \
+ CPU_PLL_DITHER_NFRAC_STEP_LSB)
+#define CPU_PLL_DITHER_NFRAC_STEP_SET(x) \
+ (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & \
+ CPU_PLL_DITHER_NFRAC_STEP_MASK)
+#define CPU_PLL_DITHER_NFRAC_STEP_RESET 1
+#define CPU_PLL_DITHER_NFRAC_MIN_MSB 11
+#define CPU_PLL_DITHER_NFRAC_MIN_LSB 6
+#define CPU_PLL_DITHER_NFRAC_MIN_MASK 0x00000fc0
+#define CPU_PLL_DITHER_NFRAC_MIN_GET(x) \
+ (((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB)
+#define CPU_PLL_DITHER_NFRAC_MIN_SET(x) \
+ (((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK)
+#define CPU_PLL_DITHER_NFRAC_MIN_RESET 3
+#define CPU_PLL_DITHER_NFRAC_MAX_MSB 5
+#define CPU_PLL_DITHER_NFRAC_MAX_LSB 0
+#define CPU_PLL_DITHER_NFRAC_MAX_MASK 0x0000003f
+#define CPU_PLL_DITHER_NFRAC_MAX_GET(x) \
+ (((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB)
+#define CPU_PLL_DITHER_NFRAC_MAX_SET(x) \
+ (((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK)
+#define CPU_PLL_DITHER_NFRAC_MAX_RESET 60
+#define CPU_PLL_DITHER_ADDRESS 0x0048
+#define CPU_PLL_DITHER_OFFSET 0x0048
+/* SW modifiable bits */
+#define CPU_PLL_DITHER_SW_MASK 0x80ffffff
+/* bits defined at reset */
+#define CPU_PLL_DITHER_RSTMASK 0xffffffff
+/* reset value (ignore bits undefined at reset) */
+#define CPU_PLL_DITHER_RESET 0x005010fc
+
+/* 32'h180600b0 (RST_BOOTSTRAP) */
+#define RST_BOOTSTRAP_USB_MODE_MSB 7
+#define RST_BOOTSTRAP_USB_MODE_LSB 7
+#define RST_BOOTSTRAP_USB_MODE_MASK 0x00000080
+#define RST_BOOTSTRAP_USB_MODE_GET(x) \
+ (((x) & RST_BOOTSTRAP_USB_MODE_MASK) >> RST_BOOTSTRAP_USB_MODE_LSB)
+#define RST_BOOTSTRAP_USB_MODE_SET(x) \
+ (((x) << RST_BOOTSTRAP_USB_MODE_LSB) & RST_BOOTSTRAP_USB_MODE_MASK)
+#define RST_BOOTSTRAP_USB_MODE_RESET 0x0
+#define RST_BOOTSTRAP_RC_SELECT_MSB 6
+#define RST_BOOTSTRAP_RC_SELECT_LSB 6
+#define RST_BOOTSTRAP_RC_SELECT_MASK 0x00000040
+#define RST_BOOTSTRAP_RC_SELECT_GET(x) \
+ (((x) & RST_BOOTSTRAP_RC_SELECT_MASK) >> RST_BOOTSTRAP_RC_SELECT_LSB)
+#define RST_BOOTSTRAP_RC_SELECT_SET(x) \
+ (((x) << RST_BOOTSTRAP_RC_SELECT_LSB) & RST_BOOTSTRAP_RC_SELECT_MASK)
+#define RST_BOOTSTRAP_RC_SELECT_RESET 0x0
+#define RST_BOOTSTRAP_EJTAG_MODE_MSB 5
+#define RST_BOOTSTRAP_EJTAG_MODE_LSB 5
+#define RST_BOOTSTRAP_EJTAG_MODE_MASK 0x00000020
+#define RST_BOOTSTRAP_EJTAG_MODE_GET(x) \
+ (((x) & RST_BOOTSTRAP_EJTAG_MODE_MASK) >> RST_BOOTSTRAP_EJTAG_MODE_LSB)
+#define RST_BOOTSTRAP_EJTAG_MODE_SET(x) \
+ (((x) << RST_BOOTSTRAP_EJTAG_MODE_LSB) & RST_BOOTSTRAP_EJTAG_MODE_MASK)
+#define RST_BOOTSTRAP_EJTAG_MODE_RESET 0x0
+#define RST_BOOTSTRAP_REF_CLK_MSB 4
+#define RST_BOOTSTRAP_REF_CLK_LSB 4
+#define RST_BOOTSTRAP_REF_CLK_MASK 0x00000010
+#define RST_BOOTSTRAP_REF_CLK_GET(x) \
+ (((x) & RST_BOOTSTRAP_REF_CLK_MASK) >> RST_BOOTSTRAP_REF_CLK_LSB)
+#define RST_BOOTSTRAP_REF_CLK_SET(x) \
+ (((x) << RST_BOOTSTRAP_REF_CLK_LSB) & RST_BOOTSTRAP_REF_CLK_MASK)
+#define RST_BOOTSTRAP_REF_CLK_RESET 0x0
+#define RST_BOOTSTRAP_DDR_WIDTH_MSB 3
+#define RST_BOOTSTRAP_DDR_WIDTH_LSB 3
+#define RST_BOOTSTRAP_DDR_WIDTH_MASK 0x00000008
+#define RST_BOOTSTRAP_DDR_WIDTH_GET(x) \
+ (((x) & RST_BOOTSTRAP_DDR_WIDTH_MASK) >> RST_BOOTSTRAP_DDR_WIDTH_LSB)
+#define RST_BOOTSTRAP_DDR_WIDTH_SET(x) \
+ (((x) << RST_BOOTSTRAP_DDR_WIDTH_LSB) & RST_BOOTSTRAP_DDR_WIDTH_MASK)
+#define RST_BOOTSTRAP_DDR_WIDTH_RESET 0x0
+#define RST_BOOTSTRAP_BOOT_SELECT_MSB 2
+#define RST_BOOTSTRAP_BOOT_SELECT_LSB 2
+#define RST_BOOTSTRAP_BOOT_SELECT_MASK 0x00000004
+#define RST_BOOTSTRAP_BOOT_SELECT_GET(x) \
+ (((x) & RST_BOOTSTRAP_BOOT_SELECT_MASK) >> \
+ RST_BOOTSTRAP_BOOT_SELECT_LSB)
+#define RST_BOOTSTRAP_BOOT_SELECT_SET(x) \
+ (((x) << RST_BOOTSTRAP_BOOT_SELECT_LSB) & \
+ RST_BOOTSTRAP_BOOT_SELECT_MASK)
+#define RST_BOOTSTRAP_BOOT_SELECT_RESET 0x0
+#define RST_BOOTSTRAP_DDR_SELECT_MSB 0
+#define RST_BOOTSTRAP_DDR_SELECT_LSB 0
+#define RST_BOOTSTRAP_DDR_SELECT_MASK 0x00000001
+#define RST_BOOTSTRAP_DDR_SELECT_GET(x) \
+ (((x) & RST_BOOTSTRAP_DDR_SELECT_MASK) >> RST_BOOTSTRAP_DDR_SELECT_LSB)
+#define RST_BOOTSTRAP_DDR_SELECT_SET(x) \
+ (((x) << RST_BOOTSTRAP_DDR_SELECT_LSB) & RST_BOOTSTRAP_DDR_SELECT_MASK)
+#define RST_BOOTSTRAP_DDR_SELECT_RESET 0x1
+/* 0 - 25MHz 1 - 40 MHz */
+#define WASP_REF_CLK_25 (1 << 4)
+
+/* 32'h1806001c (RST_RESET) */
+#define RST_RESET_HOST_RESET_MSB 31
+#define RST_RESET_HOST_RESET_LSB 31
+#define RST_RESET_HOST_RESET_MASK 0x80000000
+#define RST_RESET_HOST_RESET_GET(x) \
+ (((x) & RST_RESET_HOST_RESET_MASK) >> RST_RESET_HOST_RESET_LSB)
+#define RST_RESET_HOST_RESET_SET(x) \
+ (((x) << RST_RESET_HOST_RESET_LSB) & RST_RESET_HOST_RESET_MASK)
+#define RST_RESET_HOST_RESET_RESET 0
+#define RST_RESET_SLIC_RESET_MSB 30
+#define RST_RESET_SLIC_RESET_LSB 30
+#define RST_RESET_SLIC_RESET_MASK 0x40000000
+#define RST_RESET_SLIC_RESET_GET(x) \
+ (((x) & RST_RESET_SLIC_RESET_MASK) >> RST_RESET_SLIC_RESET_LSB)
+#define RST_RESET_SLIC_RESET_SET(x) \
+ (((x) << RST_RESET_SLIC_RESET_LSB) & RST_RESET_SLIC_RESET_MASK)
+#define RST_RESET_SLIC_RESET_RESET 0
+#define RST_RESET_HDMA_RESET_MSB 29
+#define RST_RESET_HDMA_RESET_LSB 29
+#define RST_RESET_HDMA_RESET_MASK 0x20000000
+#define RST_RESET_HDMA_RESET_GET(x) \
+ (((x) & RST_RESET_HDMA_RESET_MASK) >> RST_RESET_HDMA_RESET_LSB)
+#define RST_RESET_HDMA_RESET_SET(x) \
+ (((x) << RST_RESET_HDMA_RESET_LSB) & RST_RESET_HDMA_RESET_MASK)
+#define RST_RESET_HDMA_RESET_RESET 1
+#define RST_RESET_EXTERNAL_RESET_MSB 28
+#define RST_RESET_EXTERNAL_RESET_LSB 28
+#define RST_RESET_EXTERNAL_RESET_MASK 0x10000000
+#define RST_RESET_EXTERNAL_RESET_GET(x) \
+ (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB)
+#define RST_RESET_EXTERNAL_RESET_SET(x) \
+ (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK)
+#define RST_RESET_EXTERNAL_RESET_RESET 0
+#define RST_RESET_RTC_RESET_MSB 27
+#define RST_RESET_RTC_RESET_LSB 27
+#define RST_RESET_RTC_RESET_MASK 0x08000000
+#define RST_RESET_RTC_RESET_GET(x) \
+ (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB)
+#define RST_RESET_RTC_RESET_SET(x) \
+ (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
+#define RST_RESET_RTC_RESET_RESET 1
+#define RST_RESET_PCIEEP_RST_INT_MSB 26
+#define RST_RESET_PCIEEP_RST_INT_LSB 26
+#define RST_RESET_PCIEEP_RST_INT_MASK 0x04000000
+#define RST_RESET_PCIEEP_RST_INT_GET(x) \
+ (((x) & RST_RESET_PCIEEP_RST_INT_MASK) >> RST_RESET_PCIEEP_RST_INT_LSB)
+#define RST_RESET_PCIEEP_RST_INT_SET(x) \
+ (((x) << RST_RESET_PCIEEP_RST_INT_LSB) & RST_RESET_PCIEEP_RST_INT_MASK)
+#define RST_RESET_PCIEEP_RST_INT_RESET 0
+#define RST_RESET_CHKSUM_ACC_RESET_MSB 25
+#define RST_RESET_CHKSUM_ACC_RESET_LSB 25
+#define RST_RESET_CHKSUM_ACC_RESET_MASK 0x02000000
+#define RST_RESET_CHKSUM_ACC_RESET_GET(x) \
+ (((x) & RST_RESET_CHKSUM_ACC_RESET_MASK) >> \
+ RST_RESET_CHKSUM_ACC_RESET_LSB)
+#define RST_RESET_CHKSUM_ACC_RESET_SET(x) \
+ (((x) << RST_RESET_CHKSUM_ACC_RESET_LSB) & \
+ RST_RESET_CHKSUM_ACC_RESET_MASK)
+#define RST_RESET_CHKSUM_ACC_RESET_RESET 0
+#define RST_RESET_FULL_CHIP_RESET_MSB 24
+#define RST_RESET_FULL_CHIP_RESET_LSB 24
+#define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000
+#define RST_RESET_FULL_CHIP_RESET_GET(x) \
+ (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> \
+ RST_RESET_FULL_CHIP_RESET_LSB)
+#define RST_RESET_FULL_CHIP_RESET_SET(x) \
+ (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & \
+ RST_RESET_FULL_CHIP_RESET_MASK)
+#define RST_RESET_FULL_CHIP_RESET_RESET 0
+#define RST_RESET_GE1_MDIO_RESET_MSB 23
+#define RST_RESET_GE1_MDIO_RESET_LSB 23
+#define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000
+#define RST_RESET_GE1_MDIO_RESET_GET(x) \
+ (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB)
+#define RST_RESET_GE1_MDIO_RESET_SET(x) \
+ (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK)
+#define RST_RESET_GE1_MDIO_RESET_RESET 1
+#define RST_RESET_GE0_MDIO_RESET_MSB 22
+#define RST_RESET_GE0_MDIO_RESET_LSB 22
+#define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000
+#define RST_RESET_GE0_MDIO_RESET_GET(x) \
+ (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB)
+#define RST_RESET_GE0_MDIO_RESET_SET(x) \
+ (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK)
+#define RST_RESET_GE0_MDIO_RESET_RESET 1
+#define RST_RESET_CPU_NMI_MSB 21
+#define RST_RESET_CPU_NMI_LSB 21
+#define RST_RESET_CPU_NMI_MASK 0x00200000
+#define RST_RESET_CPU_NMI_GET(x) \
+ (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB)
+#define RST_RESET_CPU_NMI_SET(x) \
+ (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK)
+#define RST_RESET_CPU_NMI_RESET 0
+#define RST_RESET_CPU_COLD_RESET_MSB 20
+#define RST_RESET_CPU_COLD_RESET_LSB 20
+#define RST_RESET_CPU_COLD_RESET_MASK 0x00100000
+#define RST_RESET_CPU_COLD_RESET_GET(x) \
+ (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB)
+#define RST_RESET_CPU_COLD_RESET_SET(x) \
+ (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK)
+#define RST_RESET_CPU_COLD_RESET_RESET 0
+#define RST_RESET_HOST_RESET_INT_MSB 19
+#define RST_RESET_HOST_RESET_INT_LSB 19
+#define RST_RESET_HOST_RESET_INT_MASK 0x00080000
+#define RST_RESET_HOST_RESET_INT_GET(x) \
+ (((x) & RST_RESET_HOST_RESET_INT_MASK) >> RST_RESET_HOST_RESET_INT_LSB)
+#define RST_RESET_HOST_RESET_INT_SET(x) \
+ (((x) << RST_RESET_HOST_RESET_INT_LSB) & RST_RESET_HOST_RESET_INT_MASK)
+#define RST_RESET_HOST_RESET_INT_RESET 0
+#define RST_RESET_PCIEEP_RESET_MSB 18
+#define RST_RESET_PCIEEP_RESET_LSB 18
+#define RST_RESET_PCIEEP_RESET_MASK 0x00040000
+#define RST_RESET_PCIEEP_RESET_GET(x) \
+ (((x) & RST_RESET_PCIEEP_RESET_MASK) >> RST_RESET_PCIEEP_RESET_LSB)
+#define RST_RESET_PCIEEP_RESET_SET(x) \
+ (((x) << RST_RESET_PCIEEP_RESET_LSB) & RST_RESET_PCIEEP_RESET_MASK)
+#define RST_RESET_PCIEEP_RESET_RESET 0
+#define RST_RESET_UART1_RESET_MSB 17
+#define RST_RESET_UART1_RESET_LSB 17
+#define RST_RESET_UART1_RESET_MASK 0x00020000
+#define RST_RESET_UART1_RESET_GET(x) \
+ (((x) & RST_RESET_UART1_RESET_MASK) >> RST_RESET_UART1_RESET_LSB)
+#define RST_RESET_UART1_RESET_SET(x) \
+ (((x) << RST_RESET_UART1_RESET_LSB) & RST_RESET_UART1_RESET_MASK)
+#define RST_RESET_UART1_RESET_RESET 0
+#define RST_RESET_DDR_RESET_MSB 16
+#define RST_RESET_DDR_RESET_LSB 16
+#define RST_RESET_DDR_RESET_MASK 0x00010000
+#define RST_RESET_DDR_RESET_GET(x) \
+ (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB)
+#define RST_RESET_DDR_RESET_SET(x) \
+ (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK)
+#define RST_RESET_DDR_RESET_RESET 0
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) \
+ (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> \
+ RST_RESET_USB_PHY_PLL_PWD_EXT_LSB)
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) \
+ (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & \
+ RST_RESET_USB_PHY_PLL_PWD_EXT_MASK)
+#define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0
+#define RST_RESET_NANDF_RESET_MSB 14
+#define RST_RESET_NANDF_RESET_LSB 14
+#define RST_RESET_NANDF_RESET_MASK 0x00004000
+#define RST_RESET_NANDF_RESET_GET(x) \
+ (((x) & RST_RESET_NANDF_RESET_MASK) >> RST_RESET_NANDF_RESET_LSB)
+#define RST_RESET_NANDF_RESET_SET(x) \
+ (((x) << RST_RESET_NANDF_RESET_LSB) & RST_RESET_NANDF_RESET_MASK)
+#define RST_RESET_NANDF_RESET_RESET 1
+#define RST_RESET_GE1_MAC_RESET_MSB 13
+#define RST_RESET_GE1_MAC_RESET_LSB 13
+#define RST_RESET_GE1_MAC_RESET_MASK 0x00002000
+#define RST_RESET_GE1_MAC_RESET_GET(x) \
+ (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB)
+#define RST_RESET_GE1_MAC_RESET_SET(x) \
+ (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK)
+#define RST_RESET_GE1_MAC_RESET_RESET 1
+#define RST_RESET_ETH_SWITCH_ARESET_MSB 12
+#define RST_RESET_ETH_SWITCH_ARESET_LSB 12
+#define RST_RESET_ETH_SWITCH_ARESET_MASK 0x00001000
+#define RST_RESET_ETH_SWITCH_ARESET_GET(x) \
+ (((x) & RST_RESET_ETH_SWITCH_ARESET_MASK) >> \
+ RST_RESET_ETH_SWITCH_ARESET_LSB)
+#define RST_RESET_ETH_SWITCH_ARESET_SET(x) \
+ (((x) << RST_RESET_ETH_SWITCH_ARESET_LSB) & \
+ RST_RESET_ETH_SWITCH_ARESET_MASK)
+#define RST_RESET_ETH_SWITCH_ARESET_RESET 1
+#define RST_RESET_USB_PHY_ARESET_MSB 11
+#define RST_RESET_USB_PHY_ARESET_LSB 11
+#define RST_RESET_USB_PHY_ARESET_MASK 0x00000800
+#define RST_RESET_USB_PHY_ARESET_GET(x) \
+ (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB)
+#define RST_RESET_USB_PHY_ARESET_SET(x) \
+ (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK)
+#define RST_RESET_USB_PHY_ARESET_RESET 1
+#define RST_RESET_RESERVED_MSB 10
+#define RST_RESET_RESERVED_LSB 10
+#define RST_RESET_RESERVED_MASK 0x00000400
+#define RST_RESET_RESERVED_GET(x) \
+ (((x) & RST_RESET_RESERVED_MASK) >> RST_RESET_RESERVED_LSB)
+#define RST_RESET_RESERVED_SET(x) \
+ (((x) << RST_RESET_RESERVED_LSB) & RST_RESET_RESERVED_MASK)
+#define RST_RESET_RESERVED_RESET 1
+#define RST_RESET_GE0_MAC_RESET_MSB 9
+#define RST_RESET_GE0_MAC_RESET_LSB 9
+#define RST_RESET_GE0_MAC_RESET_MASK 0x00000200
+#define RST_RESET_GE0_MAC_RESET_GET(x) \
+ (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB)
+#define RST_RESET_GE0_MAC_RESET_SET(x) \
+ (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK)
+#define RST_RESET_GE0_MAC_RESET_RESET 1
+#define RST_RESET_ETH_SWITCH_RESET_MSB 8
+#define RST_RESET_ETH_SWITCH_RESET_LSB 8
+#define RST_RESET_ETH_SWITCH_RESET_MASK 0x00000100
+#define RST_RESET_ETH_SWITCH_RESET_GET(x) \
+ (((x) & RST_RESET_ETH_SWITCH_RESET_MASK) >> \
+ RST_RESET_ETH_SWITCH_RESET_LSB)
+#define RST_RESET_ETH_SWITCH_RESET_SET(x) \
+ (((x) << RST_RESET_ETH_SWITCH_RESET_LSB) & \
+ RST_RESET_ETH_SWITCH_RESET_MASK)
+#define RST_RESET_ETH_SWITCH_RESET_RESET 1
+#define RST_RESET_PCIE_PHY_RESET_MSB 7
+#define RST_RESET_PCIE_PHY_RESET_LSB 7
+#define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080
+#define RST_RESET_PCIE_PHY_RESET_GET(x) \
+ (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB)
+#define RST_RESET_PCIE_PHY_RESET_SET(x) \
+ (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK)
+#define RST_RESET_PCIE_PHY_RESET_RESET 1
+#define RST_RESET_PCIE_RESET_MSB 6
+#define RST_RESET_PCIE_RESET_LSB 6
+#define RST_RESET_PCIE_RESET_MASK 0x00000040
+#define RST_RESET_PCIE_RESET_GET(x) \
+ (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB)
+#define RST_RESET_PCIE_RESET_SET(x) \
+ (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK)
+#define RST_RESET_PCIE_RESET_RESET 1
+#define RST_RESET_USB_HOST_RESET_MSB 5
+#define RST_RESET_USB_HOST_RESET_LSB 5
+#define RST_RESET_USB_HOST_RESET_MASK 0x00000020
+#define RST_RESET_USB_HOST_RESET_GET(x) \
+ (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB)
+#define RST_RESET_USB_HOST_RESET_SET(x) \
+ (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK)
+#define RST_RESET_USB_HOST_RESET_RESET 1
+#define RST_RESET_USB_PHY_RESET_MSB 4
+#define RST_RESET_USB_PHY_RESET_LSB 4
+#define RST_RESET_USB_PHY_RESET_MASK 0x00000010
+#define RST_RESET_USB_PHY_RESET_GET(x) \
+ (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB)
+#define RST_RESET_USB_PHY_RESET_SET(x) \
+ (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK)
+#define RST_RESET_USB_PHY_RESET_RESET 1
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) \
+ (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> \
+ RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB)
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) \
+ (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & \
+ RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK)
+#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0
+#define RST_RESET_LUT_RESET_MSB 2
+#define RST_RESET_LUT_RESET_LSB 2
+#define RST_RESET_LUT_RESET_MASK 0x00000004
+#define RST_RESET_LUT_RESET_GET(x) \
+ (((x) & RST_RESET_LUT_RESET_MASK) >> RST_RESET_LUT_RESET_LSB)
+#define RST_RESET_LUT_RESET_SET(x) \
+ (((x) << RST_RESET_LUT_RESET_LSB) & RST_RESET_LUT_RESET_MASK)
+#define RST_RESET_LUT_RESET_RESET 0
+#define RST_RESET_MBOX_RESET_MSB 1
+#define RST_RESET_MBOX_RESET_LSB 1
+#define RST_RESET_MBOX_RESET_MASK 0x00000002
+#define RST_RESET_MBOX_RESET_GET(x) \
+ (((x) & RST_RESET_MBOX_RESET_MASK) >> RST_RESET_MBOX_RESET_LSB)
+#define RST_RESET_MBOX_RESET_SET(x) \
+ (((x) << RST_RESET_MBOX_RESET_LSB) & RST_RESET_MBOX_RESET_MASK)
+#define RST_RESET_MBOX_RESET_RESET 0
+#define RST_RESET_I2S_RESET_MSB 0
+#define RST_RESET_I2S_RESET_LSB 0
+#define RST_RESET_I2S_RESET_MASK 0x00000001
+#define RST_RESET_I2S_RESET_GET(x) \
+ (((x) & RST_RESET_I2S_RESET_MASK) >> RST_RESET_I2S_RESET_LSB)
+#define RST_RESET_I2S_RESET_SET(x) \
+ (((x) << RST_RESET_I2S_RESET_LSB) & RST_RESET_I2S_RESET_MASK)
+#define RST_RESET_I2S_RESET_RESET 0
+#define RST_RESET_ADDRESS 0x1806001c
+#define RST_RESET_OFFSET 0x001c
+/* SW modifiable bits */
+#define RST_RESET_SW_MASK 0xffffffff
+/* bits defined at reset */
+#define RST_RESET_RSTMASK 0xffffffff
+/* reset value (ignore bits undefined at reset) */
+#define RST_RESET_RESET 0x28c07ff0
+
+/* 32'h181161c0 (CPU_DPLL1) */
+#define CPU_DPLL1_REFDIV_MSB 31
+#define CPU_DPLL1_REFDIV_LSB 27
+#define CPU_DPLL1_REFDIV_MASK 0xf8000000
+#define CPU_DPLL1_REFDIV_GET(x) \
+ (((x) & CPU_DPLL1_REFDIV_MASK) >> CPU_DPLL1_REFDIV_LSB)
+#define CPU_DPLL1_REFDIV_SET(x) \
+ (((x) << CPU_DPLL1_REFDIV_LSB) & CPU_DPLL1_REFDIV_MASK)
+#define CPU_DPLL1_REFDIV_RESET 0x0
+#define CPU_DPLL1_NINT_MSB 26
+#define CPU_DPLL1_NINT_LSB 18
+#define CPU_DPLL1_NINT_MASK 0x07fc0000
+#define CPU_DPLL1_NINT_GET(x) \
+ (((x) & CPU_DPLL1_NINT_MASK) >> CPU_DPLL1_NINT_LSB)
+#define CPU_DPLL1_NINT_SET(x) \
+ (((x) << CPU_DPLL1_NINT_LSB) & CPU_DPLL1_NINT_MASK)
+#define CPU_DPLL1_NINT_RESET 0x0
+#define CPU_DPLL1_NFRAC_MSB 17
+#define CPU_DPLL1_NFRAC_LSB 0
+#define CPU_DPLL1_NFRAC_MASK 0x0003ffff
+#define CPU_DPLL1_NFRAC_GET(x) \
+ (((x) & CPU_DPLL1_NFRAC_MASK) >> CPU_DPLL1_NFRAC_LSB)
+#define CPU_DPLL1_NFRAC_SET(x) \
+ (((x) << CPU_DPLL1_NFRAC_LSB) & CPU_DPLL1_NFRAC_MASK)
+#define CPU_DPLL1_NFRAC_RESET 0x0
+
+/* 32'h181161c4 (CPU_DPLL2) */
+#define CPU_DPLL2_RANGE_MSB 31
+#define CPU_DPLL2_RANGE_LSB 31
+#define CPU_DPLL2_RANGE_MASK 0x80000000
+#define CPU_DPLL2_RANGE_GET(x) \
+ (((x) & CPU_DPLL2_RANGE_MASK) >> CPU_DPLL2_RANGE_LSB)
+#define CPU_DPLL2_RANGE_SET(x) \
+ (((x) << CPU_DPLL2_RANGE_LSB) & CPU_DPLL2_RANGE_MASK)
+#define CPU_DPLL2_RANGE_RESET 0x0
+#define CPU_DPLL2_LOCAL_PLL_MSB 30
+#define CPU_DPLL2_LOCAL_PLL_LSB 30
+#define CPU_DPLL2_LOCAL_PLL_MASK 0x40000000
+#define CPU_DPLL2_LOCAL_PLL_GET(x) \
+ (((x) & CPU_DPLL2_LOCAL_PLL_MASK) >> CPU_DPLL2_LOCAL_PLL_LSB)
+#define CPU_DPLL2_LOCAL_PLL_SET(x) \
+ (((x) << CPU_DPLL2_LOCAL_PLL_LSB) & CPU_DPLL2_LOCAL_PLL_MASK)
+#define CPU_DPLL2_LOCAL_PLL_RESET 0x0
+#define CPU_DPLL2_KI_MSB 29
+#define CPU_DPLL2_KI_LSB 26
+#define CPU_DPLL2_KI_MASK 0x3c000000
+#define CPU_DPLL2_KI_GET(x) \
+ (((x) & CPU_DPLL2_KI_MASK) >> CPU_DPLL2_KI_LSB)
+#define CPU_DPLL2_KI_SET(x) \
+ (((x) << CPU_DPLL2_KI_LSB) & CPU_DPLL2_KI_MASK)
+#define CPU_DPLL2_KI_RESET 0x4
+#define CPU_DPLL2_KD_MSB 25
+#define CPU_DPLL2_KD_LSB 19
+#define CPU_DPLL2_KD_MASK 0x03f80000
+#define CPU_DPLL2_KD_GET(x) \
+ (((x) & CPU_DPLL2_KD_MASK) >> CPU_DPLL2_KD_LSB)
+#define CPU_DPLL2_KD_SET(x) \
+ (((x) << CPU_DPLL2_KD_LSB) & CPU_DPLL2_KD_MASK)
+#define CPU_DPLL2_KD_RESET 0x0
+#define CPU_DPLL2_PLL_PWD_MSB 16
+#define CPU_DPLL2_PLL_PWD_LSB 16
+#define CPU_DPLL2_PLL_PWD_MASK 0x00010000
+#define CPU_DPLL2_PLL_PWD_GET(x) \
+ (((x) & CPU_DPLL2_PLL_PWD_MASK) >> CPU_DPLL2_PLL_PWD_LSB)
+#define CPU_DPLL2_PLL_PWD_SET(x) \
+ (((x) << CPU_DPLL2_PLL_PWD_LSB) & CPU_DPLL2_PLL_PWD_MASK)
+#define CPU_DPLL2_PLL_PWD_RESET 0x0
+#define CPU_DPLL2_OUTDIV_MSB 15
+#define CPU_DPLL2_OUTDIV_LSB 13
+#define CPU_DPLL2_OUTDIV_MASK 0x0000e000
+#define CPU_DPLL2_OUTDIV_GET(x) \
+ (((x) & CPU_DPLL2_OUTDIV_MASK) >> CPU_DPLL2_OUTDIV_LSB)
+#define CPU_DPLL2_OUTDIV_SET(x) \
+ (((x) << CPU_DPLL2_OUTDIV_LSB) & CPU_DPLL2_OUTDIV_MASK)
+#define CPU_DPLL2_OUTDIV_RESET 0x0
+#define CPU_DPLL2_RESERVED_MSB 12
+#define CPU_DPLL2_RESERVED_LSB 0
+#define CPU_DPLL2_RESERVED_MASK 0x00001fff
+#define CPU_DPLL2_RESERVED_GET(x) \
+ (((x) & CPU_DPLL2_RESERVED_MASK) >> CPU_DPLL2_RESERVED_LSB)
+#define CPU_DPLL2_RESERVED_SET(x) \
+ (((x) << CPU_DPLL2_RESERVED_LSB) & CPU_DPLL2_RESERVED_MASK)
+#define CPU_DPLL2_RESERVED_RESET 0x1e00
+
+/* 32'h181161c8 (CPU_DPLL3) */
+#define CPU_DPLL3_MEAS_AT_TXON_MSB 31
+#define CPU_DPLL3_MEAS_AT_TXON_LSB 31
+#define CPU_DPLL3_MEAS_AT_TXON_MASK 0x80000000
+#define CPU_DPLL3_MEAS_AT_TXON_GET(x) \
+ (((x) & CPU_DPLL3_MEAS_AT_TXON_MASK) >> CPU_DPLL3_MEAS_AT_TXON_LSB)
+#define CPU_DPLL3_MEAS_AT_TXON_SET(x) \
+ (((x) << CPU_DPLL3_MEAS_AT_TXON_LSB) & CPU_DPLL3_MEAS_AT_TXON_MASK)
+#define CPU_DPLL3_MEAS_AT_TXON_RESET 0x0
+#define CPU_DPLL3_DO_MEAS_MSB 30
+#define CPU_DPLL3_DO_MEAS_LSB 30
+#define CPU_DPLL3_DO_MEAS_MASK 0x40000000
+#define CPU_DPLL3_DO_MEAS_GET(x) \
+ (((x) & CPU_DPLL3_DO_MEAS_MASK) >> CPU_DPLL3_DO_MEAS_LSB)
+#define CPU_DPLL3_DO_MEAS_SET(x) \
+ (((x) << CPU_DPLL3_DO_MEAS_LSB) & CPU_DPLL3_DO_MEAS_MASK)
+#define CPU_DPLL3_DO_MEAS_RESET 0x0
+#define CPU_DPLL3_PHASE_SHIFT_MSB 29
+#define CPU_DPLL3_PHASE_SHIFT_LSB 23
+#define CPU_DPLL3_PHASE_SHIFT_MASK 0x3f800000
+#define CPU_DPLL3_PHASE_SHIFT_GET(x) \
+ (((x) & CPU_DPLL3_PHASE_SHIFT_MASK) >> CPU_DPLL3_PHASE_SHIFT_LSB)
+#define CPU_DPLL3_PHASE_SHIFT_SET(x) \
+ (((x) << CPU_DPLL3_PHASE_SHIFT_LSB) & CPU_DPLL3_PHASE_SHIFT_MASK)
+#define CPU_DPLL3_PHASE_SHIFT_RESET 0x0
+#define CPU_DPLL3_SQSUM_DVC_MSB 22
+#define CPU_DPLL3_SQSUM_DVC_LSB 3
+#define CPU_DPLL3_SQSUM_DVC_MASK 0x007ffff8
+#define CPU_DPLL3_SQSUM_DVC_GET(x) \
+ (((x) & CPU_DPLL3_SQSUM_DVC_MASK) >> CPU_DPLL3_SQSUM_DVC_LSB)
+#define CPU_DPLL3_SQSUM_DVC_SET(x) \
+ (((x) << CPU_DPLL3_SQSUM_DVC_LSB) & CPU_DPLL3_SQSUM_DVC_MASK)
+#define CPU_DPLL3_SQSUM_DVC_RESET 0x40000
+#define CPU_DPLL3_SPARE_MSB 2
+#define CPU_DPLL3_SPARE_LSB 0
+#define CPU_DPLL3_SPARE_MASK 0x00000007
+#define CPU_DPLL3_SPARE_GET(x) \
+ (((x) & CPU_DPLL3_SPARE_MASK) >> CPU_DPLL3_SPARE_LSB)
+#define CPU_DPLL3_SPARE_SET(x) \
+ (((x) << CPU_DPLL3_SPARE_LSB) & CPU_DPLL3_SPARE_MASK)
+#define CPU_DPLL3_SPARE_RESET 0x0
+
+/* 32'h181161cc (CPU_DPLL4) */
+#define CPU_DPLL4_MEAN_DVC_MSB 31
+#define CPU_DPLL4_MEAN_DVC_LSB 21
+#define CPU_DPLL4_MEAN_DVC_MASK 0xffe00000
+#define CPU_DPLL4_MEAN_DVC_GET(x) \
+ (((x) & CPU_DPLL4_MEAN_DVC_MASK) >> CPU_DPLL4_MEAN_DVC_LSB)
+#define CPU_DPLL4_MEAN_DVC_SET(x) \
+ (((x) << CPU_DPLL4_MEAN_DVC_LSB) & CPU_DPLL4_MEAN_DVC_MASK)
+#define CPU_DPLL4_MEAN_DVC_RESET 0x0
+#define CPU_DPLL4_VC_MEAS0_MSB 20
+#define CPU_DPLL4_VC_MEAS0_LSB 4
+#define CPU_DPLL4_VC_MEAS0_MASK 0x001ffff0
+#define CPU_DPLL4_VC_MEAS0_GET(x) \
+ (((x) & CPU_DPLL4_VC_MEAS0_MASK) >> CPU_DPLL4_VC_MEAS0_LSB)
+#define CPU_DPLL4_VC_MEAS0_SET(x) \
+ (((x) << CPU_DPLL4_VC_MEAS0_LSB) & CPU_DPLL4_VC_MEAS0_MASK)
+#define CPU_DPLL4_VC_MEAS0_RESET 0x0
+#define CPU_DPLL4_MEAS_DONE_MSB 3
+#define CPU_DPLL4_MEAS_DONE_LSB 3
+#define CPU_DPLL4_MEAS_DONE_MASK 0x00000008
+#define CPU_DPLL4_MEAS_DONE_GET(x) \
+ (((x) & CPU_DPLL4_MEAS_DONE_MASK) >> CPU_DPLL4_MEAS_DONE_LSB)
+#define CPU_DPLL4_MEAS_DONE_SET(x) \
+ (((x) << CPU_DPLL4_MEAS_DONE_LSB) & CPU_DPLL4_MEAS_DONE_MASK)
+#define CPU_DPLL4_MEAS_DONE_RESET 0x0
+#define CPU_DPLL4_SPARE_MSB 2
+#define CPU_DPLL4_SPARE_LSB 0
+#define CPU_DPLL4_SPARE_MASK 0x00000007
+#define CPU_DPLL4_SPARE_GET(x) \
+ (((x) & CPU_DPLL4_SPARE_MASK) >> CPU_DPLL4_SPARE_LSB)
+#define CPU_DPLL4_SPARE_SET(x) \
+ (((x) << CPU_DPLL4_SPARE_LSB) & CPU_DPLL4_SPARE_MASK)
+#define CPU_DPLL4_SPARE_RESET 0x0
+#define CPU_DPLL4_ADDRESS 0x181161cc
+
+/* 32'h18116240 (DDR_DPLL1) */
+#define DDR_DPLL1_REFDIV_MSB 31
+#define DDR_DPLL1_REFDIV_LSB 27
+#define DDR_DPLL1_REFDIV_MASK 0xf8000000
+#define DDR_DPLL1_REFDIV_GET(x) \
+ (((x) & DDR_DPLL1_REFDIV_MASK) >> DDR_DPLL1_REFDIV_LSB)
+#define DDR_DPLL1_REFDIV_SET(x) \
+ (((x) << DDR_DPLL1_REFDIV_LSB) & DDR_DPLL1_REFDIV_MASK)
+#define DDR_DPLL1_REFDIV_RESET 0x0
+#define DDR_DPLL1_NINT_MSB 26
+#define DDR_DPLL1_NINT_LSB 18
+#define DDR_DPLL1_NINT_MASK 0x07fc0000
+#define DDR_DPLL1_NINT_GET(x) \
+ (((x) & DDR_DPLL1_NINT_MASK) >> DDR_DPLL1_NINT_LSB)
+#define DDR_DPLL1_NINT_SET(x) \
+ (((x) << DDR_DPLL1_NINT_LSB) & DDR_DPLL1_NINT_MASK)
+#define DDR_DPLL1_NINT_RESET 0x0
+#define DDR_DPLL1_NFRAC_MSB 17
+#define DDR_DPLL1_NFRAC_LSB 0
+#define DDR_DPLL1_NFRAC_MASK 0x0003ffff
+#define DDR_DPLL1_NFRAC_GET(x) \
+ (((x) & DDR_DPLL1_NFRAC_MASK) >> DDR_DPLL1_NFRAC_LSB)
+#define DDR_DPLL1_NFRAC_SET(x) \
+ (((x) << DDR_DPLL1_NFRAC_LSB) & DDR_DPLL1_NFRAC_MASK)
+#define DDR_DPLL1_NFRAC_RESET 0x0
+
+/* 32'h18116244 (DDR_DPLL2) */
+#define DDR_DPLL2_RANGE_MSB 31
+#define DDR_DPLL2_RANGE_LSB 31
+#define DDR_DPLL2_RANGE_MASK 0x80000000
+#define DDR_DPLL2_RANGE_GET(x) \
+ (((x) & DDR_DPLL2_RANGE_MASK) >> DDR_DPLL2_RANGE_LSB)
+#define DDR_DPLL2_RANGE_SET(x) \
+ (((x) << DDR_DPLL2_RANGE_LSB) & DDR_DPLL2_RANGE_MASK)
+#define DDR_DPLL2_RANGE_RESET 0x0
+#define DDR_DPLL2_LOCAL_PLL_MSB 30
+#define DDR_DPLL2_LOCAL_PLL_LSB 30
+#define DDR_DPLL2_LOCAL_PLL_MASK 0x40000000
+#define DDR_DPLL2_LOCAL_PLL_GET(x) \
+ (((x) & DDR_DPLL2_LOCAL_PLL_MASK) >> DDR_DPLL2_LOCAL_PLL_LSB)
+#define DDR_DPLL2_LOCAL_PLL_SET(x) \
+ (((x) << DDR_DPLL2_LOCAL_PLL_LSB) & DDR_DPLL2_LOCAL_PLL_MASK)
+#define DDR_DPLL2_LOCAL_PLL_RESET 0x0
+#define DDR_DPLL2_KI_MSB 29
+#define DDR_DPLL2_KI_LSB 26
+#define DDR_DPLL2_KI_MASK 0x3c000000
+#define DDR_DPLL2_KI_GET(x) \
+ (((x) & DDR_DPLL2_KI_MASK) >> DDR_DPLL2_KI_LSB)
+#define DDR_DPLL2_KI_SET(x) \
+ (((x) << DDR_DPLL2_KI_LSB) & DDR_DPLL2_KI_MASK)
+#define DDR_DPLL2_KI_RESET 0x4
+#define DDR_DPLL2_KD_MSB 25
+#define DDR_DPLL2_KD_LSB 19
+#define DDR_DPLL2_KD_MASK 0x03f80000
+#define DDR_DPLL2_KD_GET(x) \
+ (((x) & DDR_DPLL2_KD_MASK) >> DDR_DPLL2_KD_LSB)
+#define DDR_DPLL2_KD_SET(x) \
+ (((x) << DDR_DPLL2_KD_LSB) & DDR_DPLL2_KD_MASK)
+#define DDR_DPLL2_KD_RESET 0x0
+#define DDR_DPLL2_PLL_PWD_MSB 16
+#define DDR_DPLL2_PLL_PWD_LSB 16
+#define DDR_DPLL2_PLL_PWD_MASK 0x00010000
+#define DDR_DPLL2_PLL_PWD_GET(x) \
+ (((x) & DDR_DPLL2_PLL_PWD_MASK) >> DDR_DPLL2_PLL_PWD_LSB)
+#define DDR_DPLL2_PLL_PWD_SET(x) \
+ (((x) << DDR_DPLL2_PLL_PWD_LSB) & DDR_DPLL2_PLL_PWD_MASK)
+#define DDR_DPLL2_PLL_PWD_RESET 0x0
+#define DDR_DPLL2_OUTDIV_MSB 15
+#define DDR_DPLL2_OUTDIV_LSB 13
+#define DDR_DPLL2_OUTDIV_MASK 0x0000e000
+#define DDR_DPLL2_OUTDIV_GET(x) \
+ (((x) & DDR_DPLL2_OUTDIV_MASK) >> DDR_DPLL2_OUTDIV_LSB)
+#define DDR_DPLL2_OUTDIV_SET(x) \
+ (((x) << DDR_DPLL2_OUTDIV_LSB) & DDR_DPLL2_OUTDIV_MASK)
+#define DDR_DPLL2_OUTDIV_RESET 0x0
+#define DDR_DPLL2_RESERVED_MSB 12
+#define DDR_DPLL2_RESERVED_LSB 0
+#define DDR_DPLL2_RESERVED_MASK 0x00001fff
+#define DDR_DPLL2_RESERVED_GET(x) \
+ (((x) & DDR_DPLL2_RESERVED_MASK) >> DDR_DPLL2_RESERVED_LSB)
+#define DDR_DPLL2_RESERVED_SET(x) \
+ (((x) << DDR_DPLL2_RESERVED_LSB) & DDR_DPLL2_RESERVED_MASK)
+#define DDR_DPLL2_RESERVED_RESET 0x1e00
+
+/* 32'h18116248 (DDR_DPLL3) */
+#define DDR_DPLL3_MEAS_AT_TXON_MSB 31
+#define DDR_DPLL3_MEAS_AT_TXON_LSB 31
+#define DDR_DPLL3_MEAS_AT_TXON_MASK 0x80000000
+#define DDR_DPLL3_MEAS_AT_TXON_GET(x) \
+ (((x) & DDR_DPLL3_MEAS_AT_TXON_MASK) >> DDR_DPLL3_MEAS_AT_TXON_LSB)
+#define DDR_DPLL3_MEAS_AT_TXON_SET(x) \
+ (((x) << DDR_DPLL3_MEAS_AT_TXON_LSB) & DDR_DPLL3_MEAS_AT_TXON_MASK)
+#define DDR_DPLL3_MEAS_AT_TXON_RESET 0x0
+#define DDR_DPLL3_DO_MEAS_MSB 30
+#define DDR_DPLL3_DO_MEAS_LSB 30
+#define DDR_DPLL3_DO_MEAS_MASK 0x40000000
+#define DDR_DPLL3_DO_MEAS_GET(x) \
+ (((x) & DDR_DPLL3_DO_MEAS_MASK) >> DDR_DPLL3_DO_MEAS_LSB)
+#define DDR_DPLL3_DO_MEAS_SET(x) \
+ (((x) << DDR_DPLL3_DO_MEAS_LSB) & DDR_DPLL3_DO_MEAS_MASK)
+#define DDR_DPLL3_DO_MEAS_RESET 0x0
+#define DDR_DPLL3_PHASE_SHIFT_MSB 29
+#define DDR_DPLL3_PHASE_SHIFT_LSB 23
+#define DDR_DPLL3_PHASE_SHIFT_MASK 0x3f800000
+#define DDR_DPLL3_PHASE_SHIFT_GET(x) \
+ (((x) & DDR_DPLL3_PHASE_SHIFT_MASK) >> DDR_DPLL3_PHASE_SHIFT_LSB)
+#define DDR_DPLL3_PHASE_SHIFT_SET(x) \
+ (((x) << DDR_DPLL3_PHASE_SHIFT_LSB) & DDR_DPLL3_PHASE_SHIFT_MASK)
+#define DDR_DPLL3_PHASE_SHIFT_RESET 0x0
+#define DDR_DPLL3_SQSUM_DVC_MSB 22
+#define DDR_DPLL3_SQSUM_DVC_LSB 3
+#define DDR_DPLL3_SQSUM_DVC_MASK 0x007ffff8
+#define DDR_DPLL3_SQSUM_DVC_GET(x) \
+ (((x) & DDR_DPLL3_SQSUM_DVC_MASK) >> DDR_DPLL3_SQSUM_DVC_LSB)
+#define DDR_DPLL3_SQSUM_DVC_SET(x) \
+ (((x) << DDR_DPLL3_SQSUM_DVC_LSB) & DDR_DPLL3_SQSUM_DVC_MASK)
+#define DDR_DPLL3_SQSUM_DVC_RESET 0x40000
+#define DDR_DPLL3_SPARE_MSB 2
+#define DDR_DPLL3_SPARE_LSB 0
+#define DDR_DPLL3_SPARE_MASK 0x00000007
+#define DDR_DPLL3_SPARE_GET(x) \
+ (((x) & DDR_DPLL3_SPARE_MASK) >> DDR_DPLL3_SPARE_LSB)
+#define DDR_DPLL3_SPARE_SET(x) \
+ (((x) << DDR_DPLL3_SPARE_LSB) & DDR_DPLL3_SPARE_MASK)
+#define DDR_DPLL3_SPARE_RESET 0x0
+
+/* 32'h1811624c (DDR_DPLL4) */
+#define DDR_DPLL4_MEAN_DVC_MSB 31
+#define DDR_DPLL4_MEAN_DVC_LSB 21
+#define DDR_DPLL4_MEAN_DVC_MASK 0xffe00000
+#define DDR_DPLL4_MEAN_DVC_GET(x) \
+ (((x) & DDR_DPLL4_MEAN_DVC_MASK) >> DDR_DPLL4_MEAN_DVC_LSB)
+#define DDR_DPLL4_MEAN_DVC_SET(x) \
+ (((x) << DDR_DPLL4_MEAN_DVC_LSB) & DDR_DPLL4_MEAN_DVC_MASK)
+#define DDR_DPLL4_MEAN_DVC_RESET 0x0
+#define DDR_DPLL4_VC_MEAS0_MSB 20
+#define DDR_DPLL4_VC_MEAS0_LSB 4
+#define DDR_DPLL4_VC_MEAS0_MASK 0x001ffff0
+#define DDR_DPLL4_VC_MEAS0_GET(x) \
+ (((x) & DDR_DPLL4_VC_MEAS0_MASK) >> DDR_DPLL4_VC_MEAS0_LSB)
+#define DDR_DPLL4_VC_MEAS0_SET(x) \
+ (((x) << DDR_DPLL4_VC_MEAS0_LSB) & DDR_DPLL4_VC_MEAS0_MASK)
+#define DDR_DPLL4_VC_MEAS0_RESET 0x0
+#define DDR_DPLL4_MEAS_DONE_MSB 3
+#define DDR_DPLL4_MEAS_DONE_LSB 3
+#define DDR_DPLL4_MEAS_DONE_MASK 0x00000008
+#define DDR_DPLL4_MEAS_DONE_GET(x) \
+ (((x) & DDR_DPLL4_MEAS_DONE_MASK) >> DDR_DPLL4_MEAS_DONE_LSB)
+#define DDR_DPLL4_MEAS_DONE_SET(x) \
+ (((x) << DDR_DPLL4_MEAS_DONE_LSB) & DDR_DPLL4_MEAS_DONE_MASK)
+#define DDR_DPLL4_MEAS_DONE_RESET 0x0
+#define DDR_DPLL4_SPARE_MSB 2
+#define DDR_DPLL4_SPARE_LSB 0
+#define DDR_DPLL4_SPARE_MASK 0x00000007
+#define DDR_DPLL4_SPARE_GET(x) \
+ (((x) & DDR_DPLL4_SPARE_MASK) >> DDR_DPLL4_SPARE_LSB)
+#define DDR_DPLL4_SPARE_SET(x) \
+ (((x) << DDR_DPLL4_SPARE_LSB) & DDR_DPLL4_SPARE_MASK)
+#define DDR_DPLL4_SPARE_RESET 0x0
+
+/* 32'h18116c40 (PMU1) */
+#define PMU1_INIT_VAL 0x633c8176
+
+/* 32'h18116c44 (PMU2) */
+#define PMU2_RES_MSB 31
+#define PMU2_RES_LSB 26
+#define PMU2_RES_MASK 0xfc000000
+#define PMU2_RES_GET(x) \
+ (((x) & PMU2_RES_MASK) >> PMU2_RES_LSB)
+#define PMU2_RES_SET(x) \
+ (((x) << PMU2_RES_LSB) & PMU2_RES_MASK)
+#define PMU2_RES_RESET 0x4
+#define PMU2_DISC_MSB 25
+#define PMU2_DISC_LSB 25
+#define PMU2_DISC_MASK 0x02000000
+#define PMU2_DISC_GET(x) \
+ (((x) & PMU2_DISC_MASK) >> PMU2_DISC_LSB)
+#define PMU2_DISC_SET(x) \
+ (((x) << PMU2_DISC_LSB) & PMU2_DISC_MASK)
+#define PMU2_DISC_RESET 0x0
+#define PMU2_PGM_MSB 21
+#define PMU2_PGM_LSB 21
+#define PMU2_PGM_MASK 0x00200000
+#define PMU2_PGM_GET(x) \
+ (((x) & PMU2_PGM_MASK) >> PMU2_PGM_LSB)
+#define PMU2_PGM_SET(x) \
+ (((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK)
+#define PMU2_PGM_RESET 0x1
+#define PMU2_LDO_TUNE_MSB 20
+#define PMU2_LDO_TUNE_LSB 19
+#define PMU2_LDO_TUNE_MASK 0x00180000
+#define PMU2_LDO_TUNE_GET(x) \
+ (((x) & PMU2_LDO_TUNE_MASK) >> PMU2_LDO_TUNE_LSB)
+#define PMU2_LDO_TUNE_SET(x) \
+ (((x) << PMU2_LDO_TUNE_LSB) & PMU2_LDO_TUNE_MASK)
+#define PMU2_PWDLDO_DDR_MSB 18
+#define PMU2_PWDLDO_DDR_LSB 18
+#define PMU2_PWDLDO_DDR_MASK 0x00040000
+#define PMU2_PWDLDO_DDR_GET(x) \
+ (((x) & PMU2_PWDLDO_DDR_MASK) >> PMU2_PWDLDO_DDR_LSB)
+#define PMU2_PWDLDO_DDR_SET(x) \
+ (((x) << PMU2_PWDLDO_DDR_LSB) & PMU2_PWDLDO_DDR_MASK)
+#define PMU2_PWDLDO_DDR_RESET 0x0
+
+#endif /* _AR934X_SOC_H */
--
1.8.3.2
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