[U-Boot] [PATCH RFC 5/7] WPJ344: Add support for WPJ344 board

Nikolaos Pasaloukos Nikolaos.Pasaloukos at imgtec.com
Fri Nov 29 10:48:06 CET 2013


Add support for wpj344 board and low level initialization

Signed-off-by: Nikolaos Pasaloukos <Nikolaos.Pasaloukos at imgtec.com>
---
 board/wpj344/Makefile              |    7 +
 board/wpj344/ar934x_cpu_freq_pll.h | 1138 ++++++++++++++++++++++++++++++++++++
 board/wpj344/lowlevel_init.S       |  357 +++++++++++
 board/wpj344/wpj344.c              |  149 +++++
 boards.cfg                         |    1 +
 include/configs/wpj344.h           |  171 ++++++
 6 files changed, 1823 insertions(+)
 create mode 100644 board/wpj344/Makefile
 create mode 100644 board/wpj344/ar934x_cpu_freq_pll.h
 create mode 100644 board/wpj344/lowlevel_init.S
 create mode 100644 board/wpj344/wpj344.c
 create mode 100644 include/configs/wpj344.h

diff --git a/board/wpj344/Makefile b/board/wpj344/Makefile
new file mode 100644
index 0000000..b6bbcdd
--- /dev/null
+++ b/board/wpj344/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013 Imagination Technologies
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y				= wpj344.o lowlevel_init.o
diff --git a/board/wpj344/ar934x_cpu_freq_pll.h b/board/wpj344/ar934x_cpu_freq_pll.h
new file mode 100644
index 0000000..a432234
--- /dev/null
+++ b/board/wpj344/ar934x_cpu_freq_pll.h
@@ -0,0 +1,1138 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ *
+ * Derived from works by OpenWRT
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _AR934X_CPU_FREQ_PLL_H
+#define _AR934X_CPU_FREQ_PLL_H
+
+#if (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_400_400_200)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(32)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(20)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(1)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(32)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_400_200_200)
+
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(32)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(20)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(1)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(32)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(2)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(2)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_300_300_150)
+
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(1)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(24)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(15)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_1_2G_400_200)
+#define CPU_PLL_CONFIG_NINT_VAL			CPU_PLL_CONFIG_NINT_SET(48)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(1)
+
+#define DDR_PLL_CONFIG_NINT_VAL			DDR_PLL_CONFIG_NINT_SET(32)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_500_1G_250)
+#define CPU_PLL_CONFIG_NINT_VAL			CPU_PLL_CONFIG_NINT_SET(48)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(1)
+
+#define DDR_PLL_CONFIG_NINT_VAL			DDR_PLL_CONFIG_NINT_SET(40)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_550_1_1G_275)
+#define CPU_PLL_CONFIG_NINT_VAL			CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL			DDR_PLL_CONFIG_NINT_SET(44)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_400_200)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(32)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_332_166)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(26)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(16)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_332_200)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(26)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(16)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_266_133)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(21)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(16)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_266_200)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(21)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(16)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_566_550_275)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(22)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(14)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(22)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(13)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(768) | DDR_PLL_DITHER_NFRAC_MAX_SET(768)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_566_525_262)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(22)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(14)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(21)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(13)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(128) | DDR_PLL_DITHER_NFRAC_MAX_SET(128)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_566_500_250)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(22)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(14)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(12)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(512) | DDR_PLL_DITHER_NFRAC_MAX_SET(512)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_566_475_237)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(22)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(14)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(19)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(11)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(41) | CPU_PLL_DITHER_NFRAC_MAX_SET(41)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(1023)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(895) | DDR_PLL_DITHER_NFRAC_MAX_SET(1023)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_566_450_225)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(22)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(14)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(36)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(22)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(25) | CPU_PLL_DITHER_NFRAC_MAX_SET(25)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(512) | DDR_PLL_DITHER_NFRAC_MAX_SET(512)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_566_400_200)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(22)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(14)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(16)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(10)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_560_480_240)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(22)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(14)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(19)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(12)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(25) | CPU_PLL_DITHER_NFRAC_MAX_SET(25)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(204) | DDR_PLL_DITHER_NFRAC_MAX_SET(204)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_650_600_300)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(26)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(24)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_600_300)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(24)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_550_275)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(22)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_650_325)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(26)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_525_262)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(21)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_575_287)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(23)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(14)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_450_200)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(18)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_533_400_200)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(21)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(13)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(32)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(20)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_533_500_250)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(21)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(13)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(12)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(20)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_350_175)
+#define CPU_PLL_CONFIG_NINT_VAL			CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL			DDR_PLL_CONFIG_NINT_SET(28)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_300_150)
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(24)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(15)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_400_300)
+#define CPU_PLL_CONFIG_NINT_VAL			CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL			DDR_PLL_CONFIG_NINT_SET(32)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_500_400_200)
+
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(20)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(12)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(32)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(20)
+
+#define CPU_PLL_NFRAC_25			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define CPU_PLL_NFRAC_40			\
+	CPU_PLL_DITHER_NFRAC_MIN_SET(32) | CPU_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_25			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+#define DDR_PLL_NFRAC_40			\
+	DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_700_400_200)
+
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(28)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(17)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(3)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(32)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(0)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(1)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_600_500_250)
+
+#define CPU_PLL_CONFIG_NINT_VAL_25		CPU_PLL_CONFIG_NINT_SET(24)
+#define CPU_PLL_CONFIG_NINT_VAL_40		CPU_PLL_CONFIG_NINT_SET(15)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(0)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL_25		DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_NINT_VAL_40		DDR_PLL_CONFIG_NINT_SET(12)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#elif (CONFIG_SYS_PLL_FREQ == CONFIG_PLL_500_500_250)
+
+#define CPU_PLL_CONFIG_NINT_VAL			CPU_PLL_CONFIG_NINT_SET(20)
+#define CPU_PLL_CONFIG_REF_DIV_VAL		CPU_PLL_CONFIG_REFDIV_SET(1)
+#define CPU_PLL_CONFIG_RANGE_VAL		CPU_PLL_CONFIG_RANGE_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL1		CPU_PLL_CONFIG_OUTDIV_SET(1)
+#define CPU_PLL_CONFIG_OUT_DIV_VAL2		CPU_PLL_CONFIG_OUTDIV_SET(0)
+
+#define DDR_PLL_CONFIG_NINT_VAL			DDR_PLL_CONFIG_NINT_SET(20)
+#define DDR_PLL_CONFIG_REF_DIV_VAL		DDR_PLL_CONFIG_REFDIV_SET(1)
+#define DDR_PLL_CONFIG_RANGE_VAL		DDR_PLL_CONFIG_RANGE_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL1		DDR_PLL_CONFIG_OUTDIV_SET(1)
+#define DDR_PLL_CONFIG_OUT_DIV_VAL2		DDR_PLL_CONFIG_OUTDIV_SET(0)
+
+#define CPU_PLL_NFRAC_MIN_SET			CPU_PLL_DITHER_NFRAC_MIN_SET(0)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL	\
+	CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR	\
+	CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU	\
+	CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1)
+#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)
+#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV	\
+	CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)
+
+#endif
+
+#endif /* _AR934X_CPU_FREQ_PLL_H */
diff --git a/board/wpj344/lowlevel_init.S b/board/wpj344/lowlevel_init.S
new file mode 100644
index 0000000..b2e6ce1
--- /dev/null
+++ b/board/wpj344/lowlevel_init.S
@@ -0,0 +1,357 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ *
+ * Derived from works by OpenWRT
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/ar7240_addrspace.h>
+#include <asm/ar934x_reg_cfg.h>
+#include "ar934x_cpu_freq_pll.h"
+
+/*
+ * Helper macros.
+ * These Clobber t7, t8 and t9
+ */
+#define set_val(_reg, _mask, _val)		\
+	li	t7,	KSEG1ADDR(_reg);	\
+	lw	t8,	0(t7);			\
+	li	t9,	~_mask;			\
+	and	t8,	t8,	t9;		\
+	li	t9,	_val;			\
+	or	t8,	t8,	t9;		\
+	sw	t8,	0(t7)
+
+#define cpu_pll_set(_mask, _val)	\
+	set_val(AR934X_CPU_PLL_CONFIG, _mask, _val)
+
+#define ddr_pll_set(_mask, _val)	\
+	set_val(AR934X_DDR_PLL_CONFIG, _mask, _val)
+
+#define cpu_ddr_control_set(_mask, _val)	\
+	set_val(AR934X_CPU_DDR_CLOCK_CONTROL, _mask, _val)
+
+#define set_bb_pll(reg, val)		\
+	li	t7,	KSEG1ADDR(reg);	\
+	li	t8,	val;		\
+	sw	t8,	0(t7);
+
+#define set_srif_pll(reg, val)		\
+	li	t7,	KSEG1ADDR(reg);	\
+	li	t8,	val;		\
+	sw	t8,	0(t7);
+
+#define set_srif_pll_reg(reg, _r)	\
+	li	t7,	KSEG1ADDR(reg);	\
+	sw	_r,	0(t7);
+
+#define inc_loop_count(loc)		\
+	li	t9,	loc;		\
+	lw	t7,	0(t9);		\
+	addi	t7,	t7,	1;	\
+	sw	t7,	0(t9);
+
+#define clear_loop_count(loc)	\
+	li	t9,	loc;	\
+	sw	zero,	0(t9);
+
+/*
+ * first level initialization:
+ *
+ * 0) If clock cntrl reset switch is already set, we're recovering from
+ *    "divider reset"; goto 3.
+ * 1) Setup divide ratios.
+ * 2) Reset.
+ * 3) Setup pll's, wait for lock.
+ *
+ */
+
+.globl ar934x_1_dot_1_lowlevel_init
+	.type	ar934x_1_dot_1_lowlevel_init, @function
+.globl lowlevel_init
+	.type	lowlevel_init, @function
+	.text
+	.align 4
+
+ar934x_1_dot_1_lowlevel_init:
+lowlevel_init:
+
+	set_bb_pll(CPU_DPLL2_ADDRESS, 0x13210f00);
+	set_bb_pll(CPU_DPLL3_ADDRESS, 0x03000000);
+	set_bb_pll(DDR_DPLL2_ADDRESS, 0x13210f00);
+	set_bb_pll(DDR_DPLL3_ADDRESS, 0x03000000);
+	set_bb_pll(BASEBAND_DPLL3_ADDRESS, 0x03000000);
+
+	li	t5,	KSEG1ADDR(WASP_BOOTSTRAP_REG);
+	li	t6,	WASP_REF_CLK_25
+	lw	t7,	0(t5);
+	and	t6,	t7,	t6
+	beq	zero,	t6,	setup_ref25_val
+
+setup_ref40_val:
+	li	t5,	CPU_PLL_CONFIG_NINT_VAL_40
+	li	t6,	DDR_PLL_CONFIG_NINT_VAL_40
+	li	t7,	CPU_PLL_NFRAC_40
+	li	t9,	DDR_PLL_NFRAC_40
+	b	1f
+
+setup_ref25_val:
+	li	t5,	CPU_PLL_CONFIG_NINT_VAL_25
+	li	t6,	DDR_PLL_CONFIG_NINT_VAL_25
+	li	t7,	CPU_PLL_NFRAC_25
+	li	t9,	DDR_PLL_NFRAC_25
+
+1:
+	li	t4,	(CPU_PLL_DITHER_DITHER_EN_SET(0) | \
+			CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \
+			CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf));
+	or	t4,	t4,	t7
+
+	li	t8,	(CPU_PLL_CONFIG_REF_DIV_VAL | \
+			CPU_PLL_CONFIG_RANGE_VAL | \
+			CPU_PLL_CONFIG_OUT_DIV_VAL2);
+	or	t5,	t5,	t8
+
+	li	t8,	(DDR_PLL_CONFIG_REF_DIV_VAL | \
+			DDR_PLL_CONFIG_RANGE_VAL | \
+			DDR_PLL_CONFIG_OUT_DIV_VAL2);
+	or	t6,	t6,	t8
+
+	li	t3,	(DDR_PLL_DITHER_DITHER_EN_SET(0) | \
+			DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \
+			DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf));
+
+	or	t3,	t3,	t9
+
+	li	t7,	PLL_CONFIG_VAL_F
+	lw	t8,	0(t7)
+	li	t7,	PLL_MAGIC
+	beq	t7,	t8,	read_from_flash
+	nop
+	j	pll_bypass_set
+
+read_from_flash:
+	li	t7,	PLL_CONFIG_VAL_F + 4
+	lw	t5,	0(t7)
+	lw	t4,	4(t7)
+	lw	t6,	8(t7)
+	lw	t3,	12(t7)
+
+
+pll_bypass_set:
+	cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK,
+			    CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1));
+	cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK,
+			    CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1));
+	cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK,
+			    CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
+
+init_cpu_pll:
+	li	t7,	KSEG1ADDR(AR934X_CPU_PLL_CONFIG);
+	li	t8,	CPU_PLL_CONFIG_PLLPWD_SET(1)
+	or	t8,	t8,	t5
+	sw	t8,	0(t7);
+
+init_ddr_pll:
+	li	t7,	KSEG1ADDR(AR934X_DDR_PLL_CONFIG);
+	li	t8,	DDR_PLL_CONFIG_PLLPWD_SET(1)
+	or	t8,	t8,	t6
+	sw	t8,	0(t7);
+
+init_ahb_pll:
+	li	t7,	KSEG1ADDR(AR934X_CPU_DDR_CLOCK_CONTROL);
+	li	t8,	(CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | \
+			CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR | \
+			CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR | \
+			CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU | \
+			CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV | \
+			CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV | \
+			CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) | \
+			CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) | \
+			CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
+	sw	t8,	0(t7);
+
+srif_set:
+	/* See if we have to read the pll values from flash */
+	li	t7,	SRIF_PLL_CONFIG_VAL_F
+	lw	t8,	0(t7)
+	li	t7,	SRIF_PLL_MAGIC
+	beq	t7,	t8,	read_srif_from_flash
+
+	/* Use built in values, based on ref clock */
+	li	t5,	KSEG1ADDR(WASP_BOOTSTRAP_REG);
+	li	t6,	WASP_REF_CLK_25
+	lw	t7,	0(t5);
+	and	t6,	t7,	t6
+	beq	zero,	t6,	1f
+
+	/*		refdiv		nint		nfrac */
+	/* cpu freq = (40 MHz refclk/refdiv 8) * Nint */
+	li	t4,	(CPU_DPLL1_REFDIV_SET(0x8) | CPU_DPLL1_NINT_SET(112) | \
+			 CPU_DPLL1_NFRAC_RESET);
+
+	/* ddr freq = (40 MHz refclk/refdiv 8) * Nint */
+	li	t5,	(DDR_DPLL1_REFDIV_SET(0x8) | DDR_DPLL1_NINT_SET(90) | \
+			 DDR_DPLL1_NFRAC_RESET);
+	j	2f
+
+1:
+	/* cpu freq = (25 MHz refclk/refdiv 5) * Nint */
+	li	t4,	(CPU_DPLL1_REFDIV_SET(0x5) | CPU_DPLL1_NINT_SET(112) | \
+			 CPU_DPLL1_NFRAC_RESET);
+
+	/* ddr freq = (25 MHz refclk/refdiv 5) * Nint */
+	li	t5,	(DDR_DPLL1_REFDIV_SET(0x5) | DDR_DPLL1_NINT_SET(90) | \
+			 DDR_DPLL1_NFRAC_RESET);
+	j	2f
+
+read_srif_from_flash:
+	li	t7,	SRIF_PLL_CONFIG_VAL_F + 4
+	lw	t4,	0(t7);	// CPU PLL
+	lw	t5,	4(t7);	// DDR PLL
+	/* CPU */
+2:
+	clear_loop_count(ATH_CPU_COUNT_LOC);
+
+cpu_pll_is_not_locked:
+
+	inc_loop_count(ATH_CPU_COUNT_LOC);
+
+	set_srif_pll(KSEG1ADDR(CPU_DPLL2_ADDRESS),
+		     CPU_DPLL2_KI_SET(CPU_DPLL2_KI_RESET) | \
+		     CPU_DPLL2_KD_SET(0x10) | CPU_DPLL2_PLL_PWD_SET(1) | \
+		     CPU_DPLL2_RESERVED_SET(CPU_DPLL2_RESERVED_RESET));
+	set_srif_pll_reg(KSEG1ADDR(CPU_DPLL1_ADDRESS), t4);
+	set_srif_pll(KSEG1ADDR(CPU_DPLL2_ADDRESS),
+		     CPU_DPLL2_RANGE_SET(1) | CPU_DPLL2_LOCAL_PLL_SET(1) | \
+		     CPU_DPLL2_KI_SET(CPU_DPLL2_KI_RESET) | \
+		     CPU_DPLL2_KD_SET(0x10) | CPU_DPLL2_PLL_PWD_SET(1) | \
+		     CPU_DPLL2_RESERVED_SET(CPU_DPLL2_RESERVED_RESET));
+	set_srif_pll(KSEG1ADDR(CPU_DPLL3_ADDRESS),
+		     CPU_DPLL3_PHASE_SHIFT_SET(6));
+	set_srif_pll(KSEG1ADDR(CPU_DPLL2_ADDRESS),
+		     CPU_DPLL2_RANGE_SET(1) | CPU_DPLL2_LOCAL_PLL_SET(1) | \
+		     CPU_DPLL2_KI_SET(CPU_DPLL2_KI_RESET) | \
+		     CPU_DPLL2_KD_SET(0x10) | \
+		     CPU_DPLL2_RESERVED_SET(CPU_DPLL2_RESERVED_RESET));
+
+cpu_clear_do_meas1:
+	li	t7,	KSEG1ADDR(CPU_DPLL3_ADDRESS)
+	lw	t8,	0(t7)
+	li	t9,	~CPU_DPLL3_DO_MEAS_SET(1)
+	and	t8,	t8,	t9
+	sw	t8,	0(t7)
+
+cpu_set_do_meas:
+	li	t7,	KSEG1ADDR(CPU_DPLL3_ADDRESS)
+	lw	t8,	0(t7)
+	li	t9,	CPU_DPLL3_DO_MEAS_SET(1)
+	or	t8,	t8,	t9
+	sw	t8,	0(t7)
+
+	li	t7,	KSEG1ADDR(CPU_DPLL4_ADDRESS)
+cpu_wait_for_meas_done:
+	lw	t8,	0(t7)
+	andi	t8,	t8,	CPU_DPLL4_MEAS_DONE_SET(1)
+	beqz	t8,	cpu_wait_for_meas_done
+
+cpu_clear_do_meas2:
+	li	t7,	KSEG1ADDR(CPU_DPLL3_ADDRESS)
+	lw	t8,	0(t7)
+	li	t9,	~CPU_DPLL3_DO_MEAS_SET(1)
+	and	t8,	t8,	t9
+	sw	t8,	0(t7)
+
+cpu_read_sqsum_dvc:
+	li	t7,	KSEG1ADDR(CPU_DPLL3_ADDRESS)
+	lw	t8,	0(t7)
+	li	t9,	CPU_DPLL3_SQSUM_DVC_MASK
+	and	t8,	t8,	t9
+	sra	t8,	t8,	CPU_DPLL3_SQSUM_DVC_LSB
+	li	t9,	CPU_DPLL3_SQSUM_DVC_RESET
+	subu	t8,	t8,	t9
+	bgez	t8,	cpu_pll_is_not_locked
+
+	/* DDR */
+	clear_loop_count(ATH_DDR_COUNT_LOC)
+
+ddr_pll_is_not_locked:
+	inc_loop_count(ATH_DDR_COUNT_LOC)
+	set_srif_pll(KSEG1ADDR(DDR_DPLL2_ADDRESS),
+		     DDR_DPLL2_KI_SET(DDR_DPLL2_KI_RESET) | \
+		     DDR_DPLL2_KD_SET(0x10) | DDR_DPLL2_PLL_PWD_SET(1) | \
+		     DDR_DPLL2_RESERVED_SET(DDR_DPLL2_RESERVED_RESET));
+	set_srif_pll_reg(KSEG1ADDR(DDR_DPLL1_ADDRESS), t5);
+	set_srif_pll(KSEG1ADDR(DDR_DPLL2_ADDRESS),
+		     DDR_DPLL2_RANGE_SET(1) | DDR_DPLL2_LOCAL_PLL_SET(1) | \
+		     DDR_DPLL2_KI_SET(DDR_DPLL2_KI_RESET) | \
+		     DDR_DPLL2_KD_SET(0x10) | DDR_DPLL2_PLL_PWD_SET(1) | \
+		     DDR_DPLL2_RESERVED_SET(DDR_DPLL2_RESERVED_RESET));
+	set_srif_pll(KSEG1ADDR(DDR_DPLL3_ADDRESS),
+		     DDR_DPLL3_PHASE_SHIFT_SET(6));
+	set_srif_pll(KSEG1ADDR(DDR_DPLL2_ADDRESS),
+		     DDR_DPLL2_RANGE_SET(1) | DDR_DPLL2_LOCAL_PLL_SET(1) | \
+		     DDR_DPLL2_KI_SET(DDR_DPLL2_KI_RESET) | \
+		     DDR_DPLL2_KD_SET(0x10) | \
+		     DDR_DPLL2_RESERVED_SET(DDR_DPLL2_RESERVED_RESET));
+
+ddr_clear_do_meas1:
+	li	t7,	KSEG1ADDR(DDR_DPLL3_ADDRESS)
+	lw	t8,	0(t7)
+	li	t9,	~DDR_DPLL3_DO_MEAS_SET(1)
+	and	t8,	t8,	t9
+	sw	t8,	0(t7)
+
+
+ddr_set_do_meas:
+	li	t7,	KSEG1ADDR(DDR_DPLL3_ADDRESS)
+	lw	t8,	0(t7)
+	li	t9,	DDR_DPLL3_DO_MEAS_SET(1)
+	or	t8,	t8,	t9
+	sw	t8,	0(t7)
+
+	li	t7,	KSEG1ADDR(DDR_DPLL4_ADDRESS)
+ddr_wait_for_meas_done:
+	lw	t8,	0(t7)
+	andi	t8,	t8,	DDR_DPLL4_MEAS_DONE_SET(1)
+	beqz	t8,	ddr_wait_for_meas_done
+
+ddr_clear_do_meas2:
+	li	t7,	KSEG1ADDR(DDR_DPLL3_ADDRESS)
+	lw	t8,	0(t7)
+	li	t9,	~DDR_DPLL3_DO_MEAS_SET(1)
+	and	t8,	t8,	t9
+	sw	t8,	0(t7)
+
+ddr_read_sqsum_dvc:
+	li	t7,	KSEG1ADDR(DDR_DPLL3_ADDRESS)
+	lw	t8,	0(t7)
+	li	t9,	DDR_DPLL3_SQSUM_DVC_MASK
+	and	t8,	t8,	t9
+	sra	t8,	t8,	DDR_DPLL3_SQSUM_DVC_LSB
+	li	t9,	DDR_DPLL3_SQSUM_DVC_RESET
+	subu	t8,	t8,	t9
+	bgez	t8,	ddr_pll_is_not_locked
+
+pll_bypass_unset:
+	cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK,
+			    CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0));
+	cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK,
+			    CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0));
+	cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK,
+			    CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0));
+
+ddr_pll_dither_unset:
+	li	t7,	KSEG1ADDR(AR934X_DDR_PLL_DITHER);
+	sw	t3,	0(t7);
+
+cpu_pll_dither_unset:
+	li	t7,	KSEG1ADDR(AR934X_CPU_PLL_DITHER);
+	sw	t4,	0(t7);
+
+	jr ra
diff --git a/board/wpj344/wpj344.c b/board/wpj344/wpj344.c
new file mode 100644
index 0000000..5cc0dc3
--- /dev/null
+++ b/board/wpj344/wpj344.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ *
+ * Derived from works by OpenWRT
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <config.h>
+#include <version.h>
+#include <netdev.h>
+#include <spi_flash.h>
+#include <asm/ar7240_addrspace.h>
+#include <asm/ar934x_reg_cfg.h>
+
+#define unset(a)			(~(a))
+#define reset_delay()			udelay(1000);
+
+/* Memory Mapping */
+const struct ar_ddr *ar7240_ddr = (struct ar_ddr *)
+				  KSEG1ADDR(AR7240_DDR_CTL_BASE);
+const struct ar_ddr2 *ar7240_ddr2 = (struct ar_ddr2 *)
+				    KSEG1ADDR(AR7240_DDR_CTL_BASE + 0xb8);
+const struct ar_ddr_ctl *ar7240_ddr_ctl = (struct ar_ddr_ctl *)
+					 KSEG1ADDR(AR7240_DDR_CTL_BASE + 0x108);
+const struct ar_pll *ar7240_pll = (struct ar_pll *)KSEG1ADDR(AR7240_PLL_BASE);
+const struct ar_reset1 *ar7240_rst1 = (struct ar_reset1 *)
+				      KSEG1ADDR(AR7240_RESET_BASE);
+const struct ar_reset2 *ar7240_rst2 = (struct ar_reset2 *)
+				      KSEG1ADDR(AR7240_RESET_BASE + 0x90);
+#ifdef CONFIG_PCI
+const struct ar_pci_rc_phy *ar7240_pci_rc = (struct ar_pci_rc_phy *)
+					    KSEG1ADDR(AR7240_PCIE_SRIF_REGS);
+#endif
+const struct ar_spi *ar7240_spi = (struct ar_spi *)KSEG1ADDR(AR7240_SPI_BASE);
+/* End of Memory Mapping */
+
+void _machine_restart(void)
+{
+	ar_reg_rd_set(&ar7240_rst1->reset, AR7240_RESET_FULL_CHIP);
+}
+
+void wasp_gpio_config(void)
+{
+	/* disable the CLK_OBS on GPIO_4 and set GPIO4 as input */
+	ar_reg_rd_clr(AR7240_GPIO_BASE, GPIO_INPUT_ENABLE_BIT(4));
+	ar_reg_rd_clr(GPIO_OUT_FUNCTION1_ADDRESS,
+		      GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK);
+	ar_reg_rd_set(GPIO_OUT_FUNCTION1_ADDRESS,
+		      GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(0x80));
+	ar_reg_rd_set(AR7240_GPIO_BASE, GPIO_INPUT_ENABLE_BIT(4));
+}
+
+void ath_set_tuning_caps(void)
+{
+	struct __attribute__((__packed__)) ar9300_eeprom {
+		u_int8_t pad[0x28],
+			 params_for_tuning_caps[2],
+			 feature_en;
+	};
+
+	struct ar9300_eeprom *eep = (struct ar9300_eeprom *)CONFIG_SYS_WLANCAL;
+	uint32_t val;
+
+	val = 0;
+	/* checking feature enable bit 6 and caldata is valid */
+	if ((eep->feature_en & 0x40) && (eep->pad[0x0] != 0xff)) {
+		/* xtal_capin -bit 17:23 and xtag_capout -bit 24:30*/
+		val = (eep->params_for_tuning_caps[0] & 0x7f) << 17;
+		val |= (eep->params_for_tuning_caps[0] & 0x7f) << 24;
+	} else {
+		/* default when no caldata available*/
+		/* checking clock in bit 4 */
+		if (ar_reg_rd(&ar7240_rst2->bootstrap) & WASP_REF_CLK_25)
+			val = (0x1020 << 17); /*default 0x2040 for 40Mhz clock*/
+		else
+			val = (0x2040 << 17); /*default 0x4080 for 25Mhz clock*/
+	}
+	val |= (ar_reg_rd(XTAL_ADDRESS) & (((1 << 17) - 1) | (1 << 31)));
+	ar_reg_wr(XTAL_ADDRESS, val);
+	debug("Setting 0x%08x to 0x%x\n", KSEG1ADDR(XTAL_ADDRESS), val);
+
+	return;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned int reg32;
+
+	wasp_ddr_initial_config(CONFIG_DDR_REFRESH_VAL);
+
+	/* Take WMAC out of reset */
+	reg32 = ar_reg_rd(&ar7240_rst1->reset);
+	reg32 = reg32 &  ~AR7240_RESET_WMAC;
+	ar_reg_wr(&ar7240_rst1->reset, reg32);
+
+	/* Switching regulator settings */
+	ar_reg_wr(AR7240_PMU1, PMU1_INIT_VAL); /* AR_PHY_PMU1 */
+	ar_reg_wr(AR7240_PMU2, PMU2_RES_SET(PMU2_RES_RESET) | PMU2_PGM_SET(1) |
+			       PMU2_LDO_TUNE_SET(3)); /* AR_PHY_PMU2 */
+
+	wasp_gpio_config();
+
+	/* ath_set_tuning_caps reads data from relocated flash */
+	ar_reg_wr(&ar7240_spi->control, AR7240_SPI_CTRL_REMAP_DISABLE |
+					AR7240_SPI_CTRL_CLK_DIV(1));
+	/* Needed here not to mess with Ethernet clocks */
+	ath_set_tuning_caps();
+
+	return CONFIG_SYS_MEM_SIZE;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return ar934x_initialize(bis);
+}
+
+int checkboard(void)
+{
+	puts("U-boot WPJ344\n\n");
+	return 0;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_SPI_FLASH
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return ((bus == 0) && (cs <= CONFIG_SYS_MAX_FLASH_BANKS));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	uint32_t ret;
+
+	ret = ar_reg_rd(&ar7240_spi->io_control);
+	ret &= ~(1 << (15 + slave->cs));
+	ar_reg_wr(&ar7240_spi->io_control, ret);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	ar_reg_wr(&ar7240_spi->io_control, 0x70000);
+}
+#endif /* CONFIG_SPI_FLASH */
diff --git a/boards.cfg b/boards.cfg
index e742746..4de51fe 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -498,6 +498,7 @@ Active  mips        mips32         -           micronas        vct
 Active  mips        mips32         -           micronas        vct                 vct_premium_onenand                  vct:VCT_PREMIUM,VCT_ONENAND                                                                                                       -
 Active  mips        mips32         -           micronas        vct                 vct_premium_onenand_small            vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE                                                                                       -
 Active  mips        mips32         -           micronas        vct                 vct_premium_small                    vct:VCT_PREMIUM,VCT_SMALL_IMAGE                                                                                                   -
+Active  mips        mips32         ar7240      -               wpj344              wpj344                               wpj344:MIPS32,SYS_BIG_ENDIAN                                                                                                      Nikolaos Pasaloukos <Nikolaos.Pasaloukos at imgtec.com>
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1000                             dbau1x00:DBAU1000                                                                                                                 Thomas Lange <thomas at corelatus.se>
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1100                             dbau1x00:DBAU1100                                                                                                                 Thomas Lange <thomas at corelatus.se>
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1500                             dbau1x00:DBAU1500                                                                                                                 Thomas Lange <thomas at corelatus.se>
diff --git a/include/configs/wpj344.h b/include/configs/wpj344.h
new file mode 100644
index 0000000..e147049
--- /dev/null
+++ b/include/configs/wpj344.h
@@ -0,0 +1,171 @@
+/*
+ *  Copyright (C) 2013 Imagination Technologies
+ *
+ *  SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _WPJ344_CONFIG_H
+#define _WPJ344_CONFIG_H
+
+#include <asm/addrspace.h>
+
+/*
+ * System configuration
+ */
+#define DEBUG
+#define CONFIG_FLASH_BASE		0x1f000000
+#define CONFIG_SYS_UART_BASE		0x18020000
+#define CONFIG_PCI_ar934x_soc		1
+#define CONFIG_AR934X_ETH		1
+#define CONFIG_PHYLIB			1
+#define CONFIG_PHY_ATHEROS		1
+
+/*
+ * CPU Configuration
+ */
+#define CONFIG_PLL_566_450_225		0x27
+#define CONFIG_SYS_PLL_FREQ		CONFIG_PLL_566_450_225
+
+#define CONFIG_SYS_MHZ			566	/* arbitrary value */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SYS_DCACHE_SIZE		32768	/* arbitrary value */
+#define CONFIG_SYS_ICACHE_SIZE		65536	/* arbitrary value */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* arbitrary value */
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_AR7240_SPI
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_FLASH_BASE			(KSEG1 | CONFIG_FLASH_BASE)
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		128
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_SECTOR_SIZE		(64*1024)
+
+
+/*
+ * Parameters defining the location of the calibration/initialization
+ * information for the two Merlin devices.
+ * NOTE: **This will change with different flash configurations**
+ */
+
+#define CONFIG_SYS_WLANCAL			0x9fff1000
+#define CONFIG_SYS_BOARDCAL			0x9fff0000
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16
+
+/*
+ * Memory map
+ */
+/*#define CONFIG_SYS_TEXT_BASE		0x80010000  Testing version */
+#define CONFIG_SYS_TEXT_BASE		0x9F000000 /* Rom version */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* Cached addr */
+#define CONFIG_SYS_MEM_SIZE		(128 * 1024 * 1024)
+
+#define CONFIG_SYS_SRAM_BASE		0xBD000000
+#define CONFIG_SYS_SRAM_SIZE		(32 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x1000
+
+#define CONFIG_SYS_LOAD_ADDR		0x81000000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_PROMPT		"wpj344> "
+
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+/* DDR init values */
+#define DDR2_32BIT_SUPPORT			1
+#define CONFIG_NR_DRAM_BANKS			2
+
+#define CONFIG_DDR1_RD_DATA_THIS_CYCLE_VAL	0xffff
+#define CONFIG_SDRAM_RD_DATA_THIS_CYCLE_VAL	0xffffffff
+
+#if DDR2_32BIT_SUPPORT
+#define CONFIG_DDR2_RD_DATA_THIS_CYCLE_VAL	0xff		/* 32-bit */
+#else
+#define CONFIG_DDR2_RD_DATA_THIS_CYCLE_VAL	0xffff		/* 16-bit */
+#endif
+
+/* DDR settings for WASP */
+
+#define CONFIG_DDR_REFRESH_VAL		0x4270
+
+/*
+ * Serial driver
+ */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+#define CONFIG_SYS_NS16550_CLK		40000000
+#define CONFIG_SYS_NS16550_COM1		CKSEG1ADDR(CONFIG_SYS_UART_BASE)
+#define CONFIG_CONS_INDEX		1
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_ADDR			0x9f040000
+#define CONFIG_IPADDR			192.168.1.1
+#define CONFIG_SERVERIP			192.168.1.10
+#define CONFIG_RANDOM_MACADDR		1
+
+/*
+ * Booting Process
+ */
+#define CONFIG_LZMA			1
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT_PROMPT		"Autobooting in %d seconds\n, bootdelay"
+#define CONFIG_AUTOBOOT_STOP_STR	"tpl"
+#define CONFIG_BOOTCOMMAND		"bootm 0x9f680000"
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_ECHO
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_RUN
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+
+#define CONFIG_SYS_LONGHELP
+
+#endif /* _WPJ344_CONFIG_H */
-- 
1.8.3.2




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