[U-Boot] [PATCH] ARM: OMAP5: DDR3: Change io settings

[Enric Balletbo Serra]

Hi Sricharan,

2013/10/16 Sricharan R <r.sricharan at ti.com>:
> Changing the IO settings to turn on VREF_DQ and
> disable weak pullup for DQS/nDQS.
>
> Signed-off-by: Sricharan R <r.sricharan at ti.com>
> ---
>  arch/arm/include/asm/arch-omap5/omap.h |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
> index 414d37a..3c2306f 100644
> --- a/arch/arm/include/asm/arch-omap5/omap.h
> +++ b/arch/arm/include/asm/arch-omap5/omap.h
> @@ -145,9 +145,9 @@ struct s32ktimer {
>  #define DDR_IO_2_VREF_CELLS_DDR3_VALUE                         0x0
>
>  #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
> -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
> +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
>  #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
> -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
> +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
>  #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
>
>  #define EFUSE_1 0x45145100
> --
> 1.7.9.5
>
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Sorry for my ignorance, I just want to know more ...

What's the purpose of this patch ? Solves any DDR3 problem on OMAP5 ? Improves ?

Thanks in advance,
    Enric