[U-Boot] powerpc/mpc85xx: Increase image size

[Scott Wood]

On Wed, 2013-10-16 at 13:44 -0700, York Sun wrote:
> On 10/16/2013 01:41 PM, Scott Wood wrote:
> > On Wed, 2013-10-16 at 13:38 -0700, York Sun wrote:
> >> On 10/16/2013 01:33 PM, Scott Wood wrote:
> >>> On Wed, 2013-10-16 at 13:32 -0700, York Sun wrote:
> >>>> On 10/16/2013 01:29 PM, Scott Wood wrote:
> >>>>> On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote:
> >>>>>> On 10/16/2013 12:37 PM, Scott Wood wrote:
> >>>>>>> On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote:
> >>>>>>>> Are SPL and TPL boot methods immune from the size issue here?
> >>>>>>>
> >>>>>>> Sort of.  We still need to fit inside existing partition tables.
> >>>>>>>
> >>>>>>
> >>>>>> PBL boot will be broken if the image size is bigger than 512KB, right?
> >>>>>
> >>>>> It has to be even smaller than that, to make room for early data.
> >>>>>
> >>>>
> >>>> So if we go with 768KB, do we have to convert all PBL boot to SPL boot?
> >>>
> >>> Only the targets that need the extra space.
> >>>
> >>
> >> We have T4, B4 and corenet_ds using PBL boot. They most likely will
> >> exceed the 512KB soon, if not yet. It maybe easier to change all of them
> >> togther, than one by one.
> > 
> > There's no reason to change them all at once.  It doesn't make anything
> > easier; it just means you have to do a bunch of testing all at once, and
> > force a change in procedure for users on boards where it otherwise would
> > not have been required.
> 
> You are right here.
> 
> > 
> > Plus, the 512K limit is for e500v2-based chips.  Newer chips have CPC
> > for SRAM which is larger than 512K.
> > 
> 
> Hmm? T4240 has 512KB CPC.

Each CPC is 512K, but there are three of them.  Is it possible to use
more than one for SRAM, contiguously?

Still, I find it curious that T4240 has less CPC than P4080, and less
CPC than L2 cache.

-Scott