[U-Boot] powerpc/mpc85xx: Increase image size

[Kushwaha Prabhakar-B32579]

> -----Original Message-----
> From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de]
> On Behalf Of York Sun
> Sent: Thursday, October 17, 2013 4:14 AM
> To: Wood Scott-B07421
> Cc: Tom Rini; u-boot at lists.denx.de
> Subject: Re: [U-Boot] powerpc/mpc85xx: Increase image size
> 
> On 10/16/2013 02:23 PM, Scott Wood wrote:
> > On Wed, 2013-10-16 at 13:44 -0700, York Sun wrote:
> >> On 10/16/2013 01:41 PM, Scott Wood wrote:
> >>> On Wed, 2013-10-16 at 13:38 -0700, York Sun wrote:
> >>>> On 10/16/2013 01:33 PM, Scott Wood wrote:
> >>>>> On Wed, 2013-10-16 at 13:32 -0700, York Sun wrote:
> >>>>>> On 10/16/2013 01:29 PM, Scott Wood wrote:
> >>>>>>> On Wed, 2013-10-16 at 13:22 -0700, York Sun wrote:
> >>>>>>>> On 10/16/2013 12:37 PM, Scott Wood wrote:
> >>>>>>>>> On Wed, 2013-10-16 at 10:41 -0700, York Sun wrote:
> >>>>>>>>>> Are SPL and TPL boot methods immune from the size issue here?
> >>>>>>>>>
> >>>>>>>>> Sort of.  We still need to fit inside existing partition
> tables.
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>> PBL boot will be broken if the image size is bigger than 512KB,
> right?
> >>>>>>>
> >>>>>>> It has to be even smaller than that, to make room for early data.
> >>>>>>>
> >>>>>>
> >>>>>> So if we go with 768KB, do we have to convert all PBL boot to SPL
> boot?
> >>>>>
> >>>>> Only the targets that need the extra space.
> >>>>>
> >>>>
> >>>> We have T4, B4 and corenet_ds using PBL boot. They most likely will
> >>>> exceed the 512KB soon, if not yet. It maybe easier to change all of
> >>>> them togther, than one by one.
> >>>
> >>> There's no reason to change them all at once.  It doesn't make
> >>> anything easier; it just means you have to do a bunch of testing all
> >>> at once, and force a change in procedure for users on boards where
> >>> it otherwise would not have been required.
> >>
> >> You are right here.
> >>
> >>>
> >>> Plus, the 512K limit is for e500v2-based chips.  Newer chips have
> >>> CPC for SRAM which is larger than 512K.
> >>>
> >>
> >> Hmm? T4240 has 512KB CPC.
> >
> > Each CPC is 512K, but there are three of them.  Is it possible to use
> > more than one for SRAM, contiguously?
> 
> I think it is possible to use two CPC. The PBL boot method is hard-coded
> to take 512KB u-boot.bin and generate u-boot.pbl. It surely can be
> improved. My point is making a move for all concerned platforms may be
> easier for maintenance.
> 

We can go ahead with 2 stage boot loaders for SoC having < 1MB CPC.
We have already sent patch for T1040 which has 256K CPC. This same patch can be used for T4 and B4.

FYI, I have also sent one RFC for B4 with 2stage boot loader. It can be taken as full patch.

Regards,
Prabhakar