[U-Boot] [PATCH] ARM: OMAP5: DDR3: Change io settings

[Sricharan R]

Hi Brad,

On Thursday 17 October 2013 08:05 AM, Griffis, Brad wrote:
> First, Sricharan, thanks for putting together these patches and getting them posted so quickly.  I approve of the code but wanted to comment on the commit message.  Our previous (internal) thread had a hodge podge of issues, so I think there was some confusion there.  In particular this comment was not 100% accurate:
>
>> 1) The first change from 0x64656465 to 0x64646464 removes the weak pull
>>      on the DQ lines. Otherwise the DQ line was not staying at Vref when IDLE (retreats
>>      to ground) and because of this there were extra transitions and noise.
> It removes the weak pullup, yes.  However, the DQ line not staying at VREF during IDLE was a different thing altogether and is not affected by this change.  That's actually something that is hard-coded as part of the integration of the PHY into the SoC and is not configurable...
>
> This particular pullup affects both DQS and nDQS.  We don't want to pull differential signals in the same direction.  So, bottom line, disabling that weak pullup will improve the signal integrity.  (I think I would leave the commit message at that.)
>
>>  2) The second change was to enable internal VREF_DQ_OUT which otherwise was at 0V.
> The above description is entirely accurate and I would agree is suitable for the commit message.  Here's a bit more detail for the archives...
>
> On the uEVM there are 4 DDR3 devices.  The VREF for 2 of the devices is powered by the OMAP's VREF_CA_OUT pins.  The VREF on the other 2 devices is powered by the OMAP's VREF_DQ_OUT pins.  So the net effect here is that only half of the DDR3 devices were being supplied a VREF!  This was clearly a mistake.  This patch improves the robustness of the interface and was specifically seen to cure corruption observed at high temperatures on some boards.
 Thanks for the accurate explanation, i will reword it with your suggestions above.

Regards,
 Sricharan