[U-Boot] [PATCH] powerpc/mpc8xxx: Fix CamelCase for DDR code

sun york-R58495 R58495 at freescale.com
Wed Sep 11 06:24:27 CEST 2013


Aha! I was looking for it. I remember I saw it. Thanks for the link.

York


On Sep 10, 2013, at 9:12 PM, Jain Priyanka-B32167 wrote:

> Hello York,
> 
> I have already send a similar patch:  http://patchwork.ozlabs.org/patch/271670/
> 
> Regards
> Priyanka
> 
> 
> 
>> -----Original Message-----
>> From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de]
>> On Behalf Of York Sun
>> Sent: Wednesday, September 11, 2013 1:56 AM
>> To: u-boot at lists.denx.de
>> Cc: sun york-R58495
>> Subject: [U-Boot] [PATCH] powerpc/mpc8xxx: Fix CamelCase for DDR code
>> 
>> Clean up CamelCase in DDR code to comply with latest coding style.
>> 
>> Signed-off-by: York Sun <yorksun at freescale.com>
>> ---
>> .../powerpc/cpu/mpc8xxx/ddr/common_timing_params.h |    8 ++--
>> arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c           |   46 ++++++++++----
>> ------
>> arch/powerpc/cpu/mpc8xxx/ddr/ddr.h                 |    2 +-
>> arch/powerpc/cpu/mpc8xxx/ddr/interactive.c         |   46 ++++++++++----
>> ------
>> .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c        |   14 +++---
>> arch/powerpc/cpu/mpc8xxx/ddr/main.c                |    6 +--
>> arch/powerpc/cpu/mpc8xxx/ddr/options.c             |   34 +++++++-------
>> -
>> arch/powerpc/include/asm/fsl_ddr_sdram.h           |   28 ++++++------
>> board/exmeritus/hww1u1a/ddr.c                      |    2 +-
>> board/freescale/b4860qds/ddr.c                     |    4 +-
>> board/freescale/corenet_ds/ddr.c                   |    4 +-
>> board/freescale/mpc8349emds/ddr.c                  |    6 +--
>> board/freescale/mpc8540ads/ddr.c                   |    2 +-
>> board/freescale/mpc8544ds/ddr.c                    |    2 +-
>> board/freescale/mpc8560ads/ddr.c                   |    2 +-
>> board/freescale/mpc8572ds/ddr.c                    |    4 +-
>> board/freescale/mpc8610hpcd/ddr.c                  |    2 +-
>> board/freescale/mpc8641hpcn/ddr.c                  |    2 +-
>> board/freescale/p1022ds/ddr.c                      |    4 +-
>> board/freescale/p2020ds/ddr.c                      |    4 +-
>> board/freescale/p2041rdb/ddr.c                     |    4 +-
>> board/freescale/t4qds/ddr.c                        |    4 +-
>> board/stx/stxgp3/ddr.c                             |    2 +-
>> board/stx/stxssa/ddr.c                             |    2 +-
>> board/xes/xpedite550x/ddr.c                        |    2 +-
>> doc/README.fsl-ddr                                 |    2 +-
>> 26 files changed, 119 insertions(+), 119 deletions(-)
>> 
>> diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
>> b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
>> index 06706ed..b392cd1 100644
>> --- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
>> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
>> @@ -41,10 +41,10 @@ typedef struct {
>> 	unsigned int lowest_common_SPD_caslat;
>> 	unsigned int highest_common_derated_caslat;
>> 	unsigned int additive_latency;
>> -	unsigned int all_DIMMs_burst_lengths_bitmask;
>> -	unsigned int all_DIMMs_registered;
>> -	unsigned int all_DIMMs_unbuffered;
>> -	unsigned int all_DIMMs_ECC_capable;
>> +	unsigned int all_dimms_burst_lengths_bitmask;
>> +	unsigned int all_dimms_registered;
>> +	unsigned int all_dimms_unbuffered;
>> +	unsigned int all_dimms_ecc_capable;
>> 
>> 	unsigned long long total_mem;
>> 	unsigned long long base_address;
>> diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
>> b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
>> index 242eb47..6c5dcb4 100644
>> --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
>> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
>> @@ -360,7 +360,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
>> 	ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
>> 	/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
>> 	ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
>> -		(popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
>> +		(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
>> 
>> 	ddr->timing_cfg_3 = (0
>> 		| ((ext_pretoact & 0x1) << 28)
>> @@ -440,7 +440,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
>> 		printf("Error: WRREC doesn't support more than 16 clocks\n");
>> 	else
>> 		wrrec_mclk = wrrec_table[wrrec_mclk - 1];
>> -	if (popts->OTF_burst_chop_en)
>> +	if (popts->otf_burst_chop_en)
>> 		wrrec_mclk += 2;
>> 
>> 	acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
>> @@ -462,7 +462,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
>> 	if (wrtord_mclk < 4)
>> 		wrtord_mclk = 4;
>> #endif
>> -	if (popts->OTF_burst_chop_en)
>> +	if (popts->otf_burst_chop_en)
>> 		wrtord_mclk += 2;
>> 
>> 	ddr->timing_cfg_1 = (0
>> @@ -531,12 +531,12 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t
>> *ddr,  #endif
>> 	if (additive_latency)
>> 		rd_to_pre += additive_latency;
>> -	if (popts->OTF_burst_chop_en)
>> +	if (popts->otf_burst_chop_en)
>> 		rd_to_pre += 2; /* according to UM */
>> 
>> 	wr_data_delay = popts->write_data_delay;
>> -	cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
>> -	four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
>> +	cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
>> +	four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
>> 
>> 	ddr->timing_cfg_2 = (0
>> 		| ((add_lat_mclk & 0xf) << 28)
>> @@ -555,8 +555,8 @@ static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t
>> *ddr,
>> 			       const memctl_options_t *popts,
>> 			       const common_timing_params_t *common_dimm)  {
>> -	if (common_dimm->all_DIMMs_registered
>> -		&& !common_dimm->all_DIMMs_unbuffered) {
>> +	if (common_dimm->all_dimms_registered &&
>> +	    !common_dimm->all_dimms_unbuffered) {
>> 		if (popts->rcw_override) {
>> 			ddr->ddr_sdram_rcw_1 = popts->rcw_1;
>> 			ddr->ddr_sdram_rcw_2 = popts->rcw_2; @@ -599,8 +599,8
>> @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
>> 	unsigned int dbw;		/* DRAM dta bus width */
>> 	unsigned int eight_be = 0;	/* 8-beat burst enable, DDR2 is zero
>> */
>> 	unsigned int ncap = 0;		/* Non-concurrent auto-precharge */
>> -	unsigned int threeT_en;		/* Enable 3T timing */
>> -	unsigned int twoT_en;		/* Enable 2T timing */
>> +	unsigned int three_t_en;		/* Enable 3T timing */
>> +	unsigned int two_t_en;		/* Enable 2T timing */
>> 	unsigned int ba_intlv_ctl;	/* Bank (CS) interleaving control */
>> 	unsigned int x32_en = 0;	/* x32 enable */
>> 	unsigned int pchb8 = 0;		/* precharge bit 8 enable */
>> @@ -610,20 +610,20 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t
>> *ddr,
>> 
>> 	mem_en = 1;
>> 	sren = popts->self_refresh_in_sleep;
>> -	if (common_dimm->all_DIMMs_ECC_capable) {
>> +	if (common_dimm->all_dimms_ecc_capable) {
>> 		/* Allow setting of ECC only if all DIMMs are ECC. */
>> -		ecc_en = popts->ECC_mode;
>> +		ecc_en = popts->ecc_mode;
>> 	} else {
>> 		ecc_en = 0;
>> 	}
>> 
>> -	if (common_dimm->all_DIMMs_registered
>> -		&& !common_dimm->all_DIMMs_unbuffered) {
>> +	if (common_dimm->all_dimms_registered &&
>> +	    !common_dimm->all_dimms_unbuffered) {
>> 		rd_en = 1;
>> -		twoT_en = 0;
>> +		two_t_en = 0;
>> 	} else {
>> 		rd_en = 0;
>> -		twoT_en = popts->twoT_en;
>> +		two_t_en = popts->two_t_en;
>> 	}
>> 
>> 	sdram_type = CONFIG_FSL_SDRAM_TYPE;
>> @@ -643,7 +643,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t
>> *ddr,
>> 			eight_be = 1;
>> 	}
>> 
>> -	threeT_en = popts->threeT_en;
>> +	three_t_en = popts->three_t_en;
>> 	ba_intlv_ctl = popts->ba_intlv_ctl;
>> 	hse = popts->half_strength_driver_enable;
>> 
>> @@ -657,8 +657,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t
>> *ddr,
>> 			| ((dbw & 0x3) << 19)
>> 			| ((eight_be & 0x1) << 18)
>> 			| ((ncap & 0x1) << 17)
>> -			| ((threeT_en & 0x1) << 16)
>> -			| ((twoT_en & 0x1) << 15)
>> +			| ((three_t_en & 0x1) << 16)
>> +			| ((two_t_en & 0x1) << 15)
>> 			| ((ba_intlv_ctl & 0x7F) << 8)
>> 			| ((x32_en & 0x1) << 5)
>> 			| ((pchb8 & 0x1) << 4)
>> @@ -691,7 +691,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t
>> *ddr,
>> 	int i;
>> 
>> 	dll_rst_dis = 1;	/* Make this configurable */
>> -	dqs_cfg = popts->DQS_config;
>> +	dqs_cfg = popts->qds_config;
>> 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
>> 		if (popts->cs_local_opts[i].odt_rd_cfg
>> 			|| popts->cs_local_opts[i].odt_wr_cfg) { @@ -710,7
>> +710,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
>> 	 *      << DDR_SDRAM_INTERVAL[REFINT]
>> 	 */
>> #if defined(CONFIG_FSL_DDR3)
>> -	obc_cfg = popts->OTF_burst_chop_en;
>> +	obc_cfg = popts->otf_burst_chop_en;
>> #else
>> 	obc_cfg = 0;
>> #endif
>> @@ -730,7 +730,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t
>> *ddr,
>> 
>> #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
>> 	/* Use the DDR controller to auto initialize memory. */
>> -	d_init = popts->ECC_init_using_memctl;
>> +	d_init = popts->ecc_init_using_memctl;
>> 	ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
>> 	debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);  #else
>> @@ -1101,7 +1101,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t
>> *ddr,  #if defined(CONFIG_FSL_DDR2)
>> 	const unsigned int mclk_ps = get_memory_clk_period_ps();  #endif
>> -	dqs_en = !popts->DQS_config;
>> +	dqs_en = !popts->qds_config;
>> 	rtt = fsl_ddr_get_rtt();
>> 
>> 	al = additive_latency;
>> diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
>> b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
>> index c173a5a..e3b414e 100644
>> --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
>> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
>> @@ -72,7 +72,7 @@ unsigned int compute_lowest_common_dimm_parameters(
>> 				const dimm_params_t *dimm_params,
>> 				common_timing_params_t *outpdimm,
>> 				unsigned int number_of_dimms);
>> -unsigned int populate_memctl_options(int all_DIMMs_registered,
>> +unsigned int populate_memctl_options(int all_dimms_registered,
>> 				memctl_options_t *popts,
>> 				dimm_params_t *pdimm,
>> 				unsigned int ctrl_num);
>> diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
>> b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
>> index 260fce5..7484d09 100644
>> --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
>> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
>> @@ -173,10 +173,10 @@ static void
>> lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
>> 		COMMON_TIMING(lowest_common_SPD_caslat),
>> 		COMMON_TIMING(highest_common_derated_caslat),
>> 		COMMON_TIMING(additive_latency),
>> -		COMMON_TIMING(all_DIMMs_burst_lengths_bitmask),
>> -		COMMON_TIMING(all_DIMMs_registered),
>> -		COMMON_TIMING(all_DIMMs_unbuffered),
>> -		COMMON_TIMING(all_DIMMs_ECC_capable),
>> +		COMMON_TIMING(all_dimms_burst_lengths_bitmask),
>> +		COMMON_TIMING(all_dimms_registered),
>> +		COMMON_TIMING(all_dimms_unbuffered),
>> +		COMMON_TIMING(all_dimms_ecc_capable),
>> 		COMMON_TIMING(total_mem),
>> 		COMMON_TIMING(base_address),
>> 	};
>> @@ -345,9 +345,9 @@ static void print_lowest_common_dimm_parameters(
>> 		COMMON_TIMING(highest_common_derated_caslat),
>> 		COMMON_TIMING(additive_latency),
>> 		COMMON_TIMING(ndimms_present),
>> -		COMMON_TIMING(all_DIMMs_registered),
>> -		COMMON_TIMING(all_DIMMs_unbuffered),
>> -		COMMON_TIMING(all_DIMMs_ECC_capable),
>> +		COMMON_TIMING(all_dimms_registered),
>> +		COMMON_TIMING(all_dimms_unbuffered),
>> +		COMMON_TIMING(all_dimms_ecc_capable),
>> 	};
>> 	static const unsigned int n_opts = ARRAY_SIZE(options);
>> 
>> @@ -358,8 +358,8 @@ static void print_lowest_common_dimm_parameters(
>> 	printf("tCKmax_ps = %u (%u MHz)\n",
>> 	       plcd_dimm_params->tCKmax_ps,
>> 	       picos_to_mhz(plcd_dimm_params->tCKmax_ps));
>> -	printf("all_DIMMs_burst_lengths_bitmask = %02X\n",
>> -	       plcd_dimm_params->all_DIMMs_burst_lengths_bitmask);
>> +	printf("all_dimms_burst_lengths_bitmask = %02X\n",
>> +	       plcd_dimm_params->all_dimms_burst_lengths_bitmask);
>> 
>> 	print_option_table(options, n_opts, plcd_dimm_params);
>> 
>> @@ -421,9 +421,9 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t
>> *pinfo,
>> 		CTRL_OPTIONS(memctl_interleaving),
>> 		CTRL_OPTIONS(memctl_interleaving_mode),
>> 		CTRL_OPTIONS(ba_intlv_ctl),
>> -		CTRL_OPTIONS(ECC_mode),
>> -		CTRL_OPTIONS(ECC_init_using_memctl),
>> -		CTRL_OPTIONS(DQS_config),
>> +		CTRL_OPTIONS(ecc_mode),
>> +		CTRL_OPTIONS(ecc_init_using_memctl),
>> +		CTRL_OPTIONS(qds_config),
>> 		CTRL_OPTIONS(self_refresh_in_sleep),
>> 		CTRL_OPTIONS(dynamic_power),
>> 		CTRL_OPTIONS(data_bus_width),
>> @@ -442,8 +442,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t
>> *pinfo,
>> 		 * These can probably be changed to 2T_EN and 3T_EN
>> 		 * (using a leading numerical character) without problem
>> 		 */
>> -		CTRL_OPTIONS(twoT_en),
>> -		CTRL_OPTIONS(threeT_en),
>> +		CTRL_OPTIONS(two_t_en),
>> +		CTRL_OPTIONS(three_t_en),
>> 		CTRL_OPTIONS(ap_en),
>> 		CTRL_OPTIONS(x4_en),
>> 		CTRL_OPTIONS(bstopre),
>> @@ -455,8 +455,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t
>> *pinfo,
>> 		CTRL_OPTIONS(rcw_2),
>> 		CTRL_OPTIONS(ddr_cdr1),
>> 		CTRL_OPTIONS(ddr_cdr2),
>> -		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
>> -		CTRL_OPTIONS(tFAW_window_four_activates_ps),
>> +		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
>> +		CTRL_OPTIONS(tfaw_window_four_activates_ps),
>> 		CTRL_OPTIONS(trwt_override),
>> 		CTRL_OPTIONS(trwt),
>> 	};
>> @@ -666,9 +666,9 @@ static void print_memctl_options(const
>> memctl_options_t *popts)
>> 		CTRL_OPTIONS(memctl_interleaving),
>> 		CTRL_OPTIONS(memctl_interleaving_mode),
>> 		CTRL_OPTIONS_HEX(ba_intlv_ctl),
>> -		CTRL_OPTIONS(ECC_mode),
>> -		CTRL_OPTIONS(ECC_init_using_memctl),
>> -		CTRL_OPTIONS(DQS_config),
>> +		CTRL_OPTIONS(ecc_mode),
>> +		CTRL_OPTIONS(ecc_init_using_memctl),
>> +		CTRL_OPTIONS(qds_config),
>> 		CTRL_OPTIONS(self_refresh_in_sleep),
>> 		CTRL_OPTIONS(dynamic_power),
>> 		CTRL_OPTIONS(data_bus_width),
>> @@ -686,8 +686,8 @@ static void print_memctl_options(const
>> memctl_options_t *popts)
>> 		 * These can probably be changed to 2T_EN and 3T_EN
>> 		 * (using a leading numerical character) without problem
>> 		 */
>> -		CTRL_OPTIONS(twoT_en),
>> -		CTRL_OPTIONS(threeT_en),
>> +		CTRL_OPTIONS(two_t_en),
>> +		CTRL_OPTIONS(three_t_en),
>> 		CTRL_OPTIONS(registered_dimm_en),
>> 		CTRL_OPTIONS(ap_en),
>> 		CTRL_OPTIONS(x4_en),
>> @@ -700,8 +700,8 @@ static void print_memctl_options(const
>> memctl_options_t *popts)
>> 		CTRL_OPTIONS(rcw_2),
>> 		CTRL_OPTIONS_HEX(ddr_cdr1),
>> 		CTRL_OPTIONS_HEX(ddr_cdr2),
>> -		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
>> -		CTRL_OPTIONS(tFAW_window_four_activates_ps),
>> +		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
>> +		CTRL_OPTIONS(tfaw_window_four_activates_ps),
>> 		CTRL_OPTIONS(trwt_override),
>> 		CTRL_OPTIONS(trwt),
>> 	};
>> diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
>> b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
>> index 56128a7..098619f 100644
>> --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
>> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
>> @@ -210,7 +210,7 @@ compute_lowest_common_dimm_parameters(const
>> dimm_params_t *dimm_params,
>> 			temp1 &= dimm_params[i].burst_lengths_bitmask;
>> 		}
>> 	}
>> -	outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
>> +	outpdimm->all_dimms_burst_lengths_bitmask = temp1;
>> 
>> 	/* Determine if all DIMMs registered buffered. */
>> 	temp1 = temp2 = 0;
>> @@ -232,19 +232,19 @@ compute_lowest_common_dimm_parameters(const
>> dimm_params_t *dimm_params,
>> 		}
>> 	}
>> 
>> -	outpdimm->all_DIMMs_registered = 0;
>> -	outpdimm->all_DIMMs_unbuffered = 0;
>> +	outpdimm->all_dimms_registered = 0;
>> +	outpdimm->all_dimms_unbuffered = 0;
>> 	if (temp1 && !temp2) {
>> -		outpdimm->all_DIMMs_registered = 1;
>> +		outpdimm->all_dimms_registered = 1;
>> 	} else if (!temp1 && temp2) {
>> -		outpdimm->all_DIMMs_unbuffered = 1;
>> +		outpdimm->all_dimms_unbuffered = 1;
>> 	} else {
>> 		printf("ERROR:  Mix of registered buffered and unbuffered "
>> 				"DIMMs detected!\n");
>> 	}
>> 
>> 	temp1 = 0;
>> -	if (outpdimm->all_DIMMs_registered)
>> +	if (outpdimm->all_dimms_registered)
>> 		for (j = 0; j < 16; j++) {
>> 			outpdimm->rcw[j] = dimm_params[0].rcw[j];
>> 			for (i = 1; i < number_of_dimms; i++) { @@ -397,7
>> +397,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t
>> *dimm_params,
>> 	} else {
>> 		debug("Warning: not all DIMMs ECC capable, cant enable
>> ECC\n");
>> 	}
>> -	outpdimm->all_DIMMs_ECC_capable = temp1;
>> +	outpdimm->all_dimms_ecc_capable = temp1;
>> 
>> #ifndef CONFIG_FSL_DDR3
>> 	/* FIXME: move to somewhere else to validate. */ diff --git
>> a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
>> b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
>> index 842bf19..b9ae950 100644
>> --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
>> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
>> @@ -457,7 +457,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int
>> start_step,
>> 			 * which is currently STEP_ASSIGN_ADDRESSES.
>> 			 */
>> 			populate_memctl_options(
>> -					timing_params[i].all_DIMMs_registered,
>> +					timing_params[i].all_dimms_registered,
>> 					&pinfo->memctl_opts[i],
>> 					pinfo->dimm_params[i], i);
>> 			/*
>> @@ -466,7 +466,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int
>> start_step,
>> 			 * using fixed parameters, this function should be
>> 			 * be called from board init file.
>> 			 */
>> -			if (timing_params[i].all_DIMMs_registered)
>> +			if (timing_params[i].all_dimms_registered)
>> 				assert_reset = 1;
>> 		}
>> 		if (assert_reset) {
>> @@ -589,7 +589,7 @@ phys_size_t fsl_ddr_sdram(void)
>> 	 */
>> 	deassert_reset = board_need_mem_reset();
>> 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
>> -		if (info.common_timing_params[i].all_DIMMs_registered)
>> +		if (info.common_timing_params[i].all_dimms_registered)
>> 			deassert_reset = 1;
>> 	}
>> 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { diff --git
>> a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
>> b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
>> index 30cdca4..67bc43b 100644
>> --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
>> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
>> @@ -499,7 +499,7 @@ static inline unsigned int
>> auto_bank_intlv(dimm_params_t *pdimm)
>> 	return 0;
>> }
>> 
>> -unsigned int populate_memctl_options(int all_DIMMs_registered,
>> +unsigned int populate_memctl_options(int all_dimms_registered,
>> 			memctl_options_t *popts,
>> 			dimm_params_t *pdimm,
>> 			unsigned int ctrl_num)
>> @@ -635,20 +635,20 @@ unsigned int populate_memctl_options(int
>> all_DIMMs_registered,
>> 	popts->ba_intlv_ctl = 0;
>> 
>> 	/* Memory Organization Parameters */
>> -	popts->registered_dimm_en = all_DIMMs_registered;
>> +	popts->registered_dimm_en = all_dimms_registered;
>> 
>> 	/* Operational Mode Paramters */
>> 
>> 	/* Pick ECC modes */
>> -	popts->ECC_mode = 0;		  /* 0 = disabled, 1 = enabled */
>> +	popts->ecc_mode = 0;		  /* 0 = disabled, 1 = enabled */
>> #ifdef CONFIG_DDR_ECC
>> 	if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
>> 		if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
>> -			popts->ECC_mode = 1;
>> +			popts->ecc_mode = 1;
>> 	} else
>> -		popts->ECC_mode = 1;
>> +		popts->ecc_mode = 1;
>> #endif
>> -	popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
>> +	popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
>> 
>> 	/*
>> 	 * Choose DQS config
>> @@ -656,9 +656,9 @@ unsigned int populate_memctl_options(int
>> all_DIMMs_registered,
>> 	 * 1 for DDR2
>> 	 */
>> #if defined(CONFIG_FSL_DDR1)
>> -	popts->DQS_config = 0;
>> +	popts->qds_config = 0;
>> #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
>> -	popts->DQS_config = 1;
>> +	popts->qds_config = 1;
>> #endif
>> 
>> 	/* Choose self-refresh during sleep. */ @@ -705,15 +705,15 @@
>> unsigned int populate_memctl_options(int all_DIMMs_registered,
>> 	/* Choose burst length. */
>> #if defined(CONFIG_FSL_DDR3)
>> #if defined(CONFIG_E500MC)
>> -	popts->OTF_burst_chop_en = 0;	/* on-the-fly burst chop disable */
>> +	popts->otf_burst_chop_en = 0;	/* on-the-fly burst chop disable */
>> 	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
>> #else
>> 	if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
>> 		/* 32-bit or 16-bit bus */
>> -		popts->OTF_burst_chop_en = 0;
>> +		popts->otf_burst_chop_en = 0;
>> 		popts->burst_length = DDR_BL8;
>> 	} else {
>> -		popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
>> +		popts->otf_burst_chop_en = 1;	/* on-the-fly burst chop */
>> 		popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8
>> */
>> 	}
>> #endif
>> @@ -756,8 +756,8 @@ unsigned int populate_memctl_options(int
>> all_DIMMs_registered,
>> 	 *	- number of components, number of active ranks
>> 	 *	- how much time you want to spend playing around
>> 	 */
>> -	popts->twoT_en = 0;
>> -	popts->threeT_en = 0;
>> +	popts->two_t_en = 0;
>> +	popts->three_t_en = 0;
>> 
>> 	/* for RDIMM, address parity enable */
>> 	popts->ap_en = 1;
>> @@ -775,7 +775,7 @@ unsigned int populate_memctl_options(int
>> all_DIMMs_registered,
>> 	popts->bstopre = 0x100;
>> 
>> 	/* Minimum CKE pulse width -- tCKE(MIN) */
>> -	popts->tCKE_clock_pulse_width_ps
>> +	popts->tcke_clock_pulse_width_ps
>> 		= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
>> 
>> 	/*
>> @@ -786,17 +786,17 @@ unsigned int populate_memctl_options(int
>> all_DIMMs_registered,
>> 	 * FIXME: width, was considering looking at pdimm-
>>> primary_sdram_width
>> 	 */
>> #if defined(CONFIG_FSL_DDR1)
>> -	popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
>> +	popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
>> 
>> #elif defined(CONFIG_FSL_DDR2)
>> 	/*
>> 	 * x4/x8;  some datasheets have 35000
>> 	 * x16 wide columns only?  Use 50000?
>> 	 */
>> -	popts->tFAW_window_four_activates_ps = 37500;
>> +	popts->tfaw_window_four_activates_ps = 37500;
>> 
>> #elif defined(CONFIG_FSL_DDR3)
>> -	popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
>> +	popts->tfaw_window_four_activates_ps = pdimm[0].tFAW_ps;
>> #endif
>> 	popts->zq_en = 0;
>> 	popts->wrlvl_en = 0;
>> diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h
>> b/arch/powerpc/include/asm/fsl_ddr_sdram.h
>> index f4eec82..29cf754 100644
>> --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
>> +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
>> @@ -219,13 +219,13 @@ typedef struct fsl_ddr_cfg_regs_s {  }
>> fsl_ddr_cfg_regs_t;
>> 
>> typedef struct memctl_options_partial_s {
>> -	unsigned int all_DIMMs_ECC_capable;
>> -	unsigned int all_DIMMs_tCKmax_ps;
>> -	unsigned int all_DIMMs_burst_lengths_bitmask;
>> -	unsigned int all_DIMMs_registered;
>> -	unsigned int all_DIMMs_unbuffered;
>> +	unsigned int all_dimms_ecc_capable;
>> +	unsigned int all_dimms_tck_max_ps;
>> +	unsigned int all_dimms_burst_lengths_bitmask;
>> +	unsigned int all_dimms_registered;
>> +	unsigned int all_dimms_unbuffered;
>> 	/*	unsigned int lowest_common_SPD_caslat; */
>> -	unsigned int all_DIMMs_minimum_tRCD_ps;
>> +	unsigned int all_dimms_minimum_trcd_ps;
>> } memctl_options_partial_t;
>> 
>> #define DDR_DATA_BUS_WIDTH_64 0
>> @@ -261,10 +261,10 @@ typedef struct memctl_options_s {
>> 	unsigned int addr_hash;
>> 
>> 	/* Operational mode parameters */
>> -	unsigned int ECC_mode;	 /* Use ECC? */
>> +	unsigned int ecc_mode;	 /* Use ECC? */
>> 	/* Initialize ECC using memory controller? */
>> -	unsigned int ECC_init_using_memctl;
>> -	unsigned int DQS_config;	/* Use DQS? maybe only with DDR2? */
>> +	unsigned int ecc_init_using_memctl;
>> +	unsigned int qds_config;	/* Use DQS? maybe only with DDR2? */
>> 	/* SREN - self-refresh during sleep */
>> 	unsigned int self_refresh_in_sleep;
>> 	unsigned int dynamic_power;	/* DYN_PWR */
>> @@ -272,7 +272,7 @@ typedef struct memctl_options_s {
>> 	unsigned int data_bus_width;
>> 	unsigned int burst_length;	/* BL4, OTF and BL8 */
>> 	/* On-The-Fly Burst Chop enable */
>> -	unsigned int OTF_burst_chop_en;
>> +	unsigned int otf_burst_chop_en;
>> 	/* mirrior DIMMs for DDR3 */
>> 	unsigned int mirrored_dimm;
>> 	unsigned int quad_rank_present;
>> @@ -297,11 +297,11 @@ typedef struct memctl_options_s {
>> 	unsigned int wrlvl_ctl_3;
>> 
>> 	unsigned int half_strength_driver_enable;
>> -	unsigned int twoT_en;
>> -	unsigned int threeT_en;
>> +	unsigned int two_t_en;
>> +	unsigned int three_t_en;
>> 	unsigned int bstopre;
>> -	unsigned int tCKE_clock_pulse_width_ps;	/* tCKE */
>> -	unsigned int tFAW_window_four_activates_ps;	/* tFAW --
>> FOUR_ACT */
>> +	unsigned int tcke_clock_pulse_width_ps;	/* tCKE */
>> +	unsigned int tfaw_window_four_activates_ps;	/* tFAW --
>> FOUR_ACT */
>> 
>> 	/* Rtt impedance */
>> 	unsigned int rtt_override;		/* rtt_override enable */
>> diff --git a/board/exmeritus/hww1u1a/ddr.c
>> b/board/exmeritus/hww1u1a/ddr.c index 36d02ad..05b8a84 100644
>> --- a/board/exmeritus/hww1u1a/ddr.c
>> +++ b/board/exmeritus/hww1u1a/ddr.c
>> @@ -30,5 +30,5 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 	popts->clk_adjust = 4;
>> 	popts->cpo_override = 4;
>> 	popts->write_data_delay = 2;
>> -	popts->twoT_en = 0;
>> +	popts->two_t_en = 0;
>> }
>> diff --git a/board/freescale/b4860qds/ddr.c
>> b/board/freescale/b4860qds/ddr.c index b82b3d4..f77a4b8 100644
>> --- a/board/freescale/b4860qds/ddr.c
>> +++ b/board/freescale/b4860qds/ddr.c
>> @@ -129,7 +129,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 				popts->wrlvl_start = pbsp->wrlvl_start;
>> 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
>> 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
>> -				popts->twoT_en = pbsp->force_2T;
>> +				popts->two_t_en = pbsp->force_2T;
>> 				goto found;
>> 			}
>> 			pbsp_highest = pbsp;
>> @@ -146,7 +146,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 		popts->write_data_delay = pbsp_highest->write_data_delay;
>> 		popts->clk_adjust = pbsp_highest->clk_adjust;
>> 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
>> -		popts->twoT_en = pbsp_highest->force_2T;
>> +		popts->two_t_en = pbsp_highest->force_2T;
>> 	} else {
>> 		panic("DIMM is not supported by this board");
>> 	}
>> diff --git a/board/freescale/corenet_ds/ddr.c
>> b/board/freescale/corenet_ds/ddr.c
>> index 517e87f..ea393cd 100644
>> --- a/board/freescale/corenet_ds/ddr.c
>> +++ b/board/freescale/corenet_ds/ddr.c
>> @@ -217,7 +217,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 					pbsp->write_data_delay;
>> 				popts->clk_adjust = pbsp->clk_adjust;
>> 				popts->wrlvl_start = pbsp->wrlvl_start;
>> -				popts->twoT_en = pbsp->force_2T;
>> +				popts->two_t_en = pbsp->force_2T;
>> 				goto found;
>> 			}
>> 			pbsp_highest = pbsp;
>> @@ -234,7 +234,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 		popts->write_data_delay = pbsp_highest->write_data_delay;
>> 		popts->clk_adjust = pbsp_highest->clk_adjust;
>> 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
>> -		popts->twoT_en = pbsp_highest->force_2T;
>> +		popts->two_t_en = pbsp_highest->force_2T;
>> 	} else {
>> 		panic("DIMM is not supported by this board");
>> 	}
>> diff --git a/board/freescale/mpc8349emds/ddr.c
>> b/board/freescale/mpc8349emds/ddr.c
>> index c66750e..85d216a 100644
>> --- a/board/freescale/mpc8349emds/ddr.c
>> +++ b/board/freescale/mpc8349emds/ddr.c
>> @@ -70,7 +70,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 				popts->cpo_override = pbsp->cpo;
>> 				popts->write_data_delay =
>> 					pbsp->write_data_delay;
>> -				popts->twoT_en = pbsp->force_2T;
>> +				popts->two_t_en = pbsp->force_2T;
>> 				goto found;
>> 			}
>> 			pbsp_highest = pbsp;
>> @@ -86,7 +86,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 		popts->clk_adjust = pbsp_highest->clk_adjust;
>> 		popts->cpo_override = pbsp_highest->cpo;
>> 		popts->write_data_delay = pbsp_highest->write_data_delay;
>> -		popts->twoT_en = pbsp_highest->force_2T;
>> +		popts->two_t_en = pbsp_highest->force_2T;
>> 	} else {
>> 		panic("DIMM is not supported by this board");
>> 	}
>> @@ -97,5 +97,5 @@ found:
>> 	 *	- number of DIMMs installed
>> 	 */
>> 	popts->half_strength_driver_enable = 0;
>> -	popts->DQS_config = 0;	/* only true DQS signal is used on board */
>> +	popts->qds_config = 0;	/* only true DQS signal is used on board */
>> }
>> diff --git a/board/freescale/mpc8540ads/ddr.c
>> b/board/freescale/mpc8540ads/ddr.c
>> index 5711374..2240972 100644
>> --- a/board/freescale/mpc8540ads/ddr.c
>> +++ b/board/freescale/mpc8540ads/ddr.c
>> @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 	popts->write_data_delay = 3;
>> 
>> 	/* 2T timing enable */
>> -	popts->twoT_en = 1;
>> +	popts->two_t_en = 1;
>> 
>> 	/*
>> 	 * Factors to consider for half-strength driver enable:
>> diff --git a/board/freescale/mpc8544ds/ddr.c
>> b/board/freescale/mpc8544ds/ddr.c index 94219b9..c76733f 100644
>> --- a/board/freescale/mpc8544ds/ddr.c
>> +++ b/board/freescale/mpc8544ds/ddr.c
>> @@ -49,7 +49,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 	popts->write_data_delay = 3;
>> 
>> 	/* 2T timing enable */
>> -	popts->twoT_en = 1;
>> +	popts->two_t_en = 1;
>> 
>> 	/*
>> 	 * Factors to consider for half-strength driver enable:
>> diff --git a/board/freescale/mpc8560ads/ddr.c
>> b/board/freescale/mpc8560ads/ddr.c
>> index 5711374..2240972 100644
>> --- a/board/freescale/mpc8560ads/ddr.c
>> +++ b/board/freescale/mpc8560ads/ddr.c
>> @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 	popts->write_data_delay = 3;
>> 
>> 	/* 2T timing enable */
>> -	popts->twoT_en = 1;
>> +	popts->two_t_en = 1;
>> 
>> 	/*
>> 	 * Factors to consider for half-strength driver enable:
>> diff --git a/board/freescale/mpc8572ds/ddr.c
>> b/board/freescale/mpc8572ds/ddr.c index a7ff668..1784932 100644
>> --- a/board/freescale/mpc8572ds/ddr.c
>> +++ b/board/freescale/mpc8572ds/ddr.c
>> @@ -139,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 				popts->cpo_override = pbsp->cpo;
>> 				popts->write_data_delay =
>> 					pbsp->write_data_delay;
>> -				popts->twoT_en = pbsp->force_2T;
>> +				popts->two_t_en = pbsp->force_2T;
>> 				goto found;
>> 			}
>> 			pbsp_highest = pbsp;
>> @@ -155,7 +155,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 		popts->clk_adjust = pbsp->clk_adjust;
>> 		popts->cpo_override = pbsp->cpo;
>> 		popts->write_data_delay = pbsp->write_data_delay;
>> -		popts->twoT_en = pbsp->force_2T;
>> +		popts->two_t_en = pbsp->force_2T;
>> 	} else {
>> 		panic("DIMM is not supported by this board");
>> 	}
>> diff --git a/board/freescale/mpc8610hpcd/ddr.c
>> b/board/freescale/mpc8610hpcd/ddr.c
>> index 94219b9..c76733f 100644
>> --- a/board/freescale/mpc8610hpcd/ddr.c
>> +++ b/board/freescale/mpc8610hpcd/ddr.c
>> @@ -49,7 +49,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 	popts->write_data_delay = 3;
>> 
>> 	/* 2T timing enable */
>> -	popts->twoT_en = 1;
>> +	popts->two_t_en = 1;
>> 
>> 	/*
>> 	 * Factors to consider for half-strength driver enable:
>> diff --git a/board/freescale/mpc8641hpcn/ddr.c
>> b/board/freescale/mpc8641hpcn/ddr.c
>> index 5d35757..b4ffef3 100644
>> --- a/board/freescale/mpc8641hpcn/ddr.c
>> +++ b/board/freescale/mpc8641hpcn/ddr.c
>> @@ -106,5 +106,5 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 
>> found:
>> 	/* 2T timing enable */
>> -	popts->twoT_en = 1;
>> +	popts->two_t_en = 1;
>> }
>> diff --git a/board/freescale/p1022ds/ddr.c
>> b/board/freescale/p1022ds/ddr.c index a639861..9e9f404 100644
>> --- a/board/freescale/p1022ds/ddr.c
>> +++ b/board/freescale/p1022ds/ddr.c
>> @@ -72,7 +72,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> dimm_params_t *pdimm,
>> 				popts->cpo_override = pbsp->cpo;
>> 				popts->write_data_delay =
>> 					pbsp->write_data_delay;
>> -				popts->twoT_en = pbsp->force_2T;
>> +				popts->two_t_en = pbsp->force_2T;
>> 				goto found;
>> 			}
>> 			pbsp_highest = pbsp;
>> @@ -88,7 +88,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> dimm_params_t *pdimm,
>> 		popts->clk_adjust = pbsp->clk_adjust;
>> 		popts->cpo_override = pbsp->cpo;
>> 		popts->write_data_delay = pbsp->write_data_delay;
>> -		popts->twoT_en = pbsp->force_2T;
>> +		popts->two_t_en = pbsp->force_2T;
>> 	} else {
>> 		panic("DIMM is not supported by this board");
>> 	}
>> diff --git a/board/freescale/p2020ds/ddr.c
>> b/board/freescale/p2020ds/ddr.c index 59034f9..51fd0b5 100644
>> --- a/board/freescale/p2020ds/ddr.c
>> +++ b/board/freescale/p2020ds/ddr.c
>> @@ -90,7 +90,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 				popts->cpo_override = pbsp->cpo;
>> 				popts->write_data_delay =
>> 					pbsp->write_data_delay;
>> -				popts->twoT_en = pbsp->force_2T;
>> +				popts->two_t_en = pbsp->force_2T;
>> 				goto found;
>> 			}
>> 			pbsp_highest = pbsp;
>> @@ -106,7 +106,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 		popts->clk_adjust = pbsp_highest->clk_adjust;
>> 		popts->cpo_override = pbsp_highest->cpo;
>> 		popts->write_data_delay = pbsp_highest->write_data_delay;
>> -		popts->twoT_en = pbsp_highest->force_2T;
>> +		popts->two_t_en = pbsp_highest->force_2T;
>> 	} else {
>> 		panic("DIMM is not supported by this board");
>> 	}
>> diff --git a/board/freescale/p2041rdb/ddr.c
>> b/board/freescale/p2041rdb/ddr.c index 6d9a5de..4d3eb99 100644
>> --- a/board/freescale/p2041rdb/ddr.c
>> +++ b/board/freescale/p2041rdb/ddr.c
>> @@ -76,7 +76,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 					pbsp->write_data_delay;
>> 				popts->clk_adjust = pbsp->clk_adjust;
>> 				popts->wrlvl_start = pbsp->wrlvl_start;
>> -				popts->twoT_en = pbsp->force_2T;
>> +				popts->two_t_en = pbsp->force_2T;
>> 				goto found;
>> 			}
>> 			pbsp_highest = pbsp;
>> @@ -93,7 +93,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 		popts->write_data_delay = pbsp_highest->write_data_delay;
>> 		popts->clk_adjust = pbsp_highest->clk_adjust;
>> 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
>> -		popts->twoT_en = pbsp_highest->force_2T;
>> +		popts->two_t_en = pbsp_highest->force_2T;
>> 	} else {
>> 		panic("DIMM is not supported by this board");
>> 	}
>> diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
>> index 26ac2a5..6ee474c 100644
>> --- a/board/freescale/t4qds/ddr.c
>> +++ b/board/freescale/t4qds/ddr.c
>> @@ -56,7 +56,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 				popts->wrlvl_start = pbsp->wrlvl_start;
>> 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
>> 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
>> -				popts->twoT_en = pbsp->force_2T;
>> +				popts->two_t_en = pbsp->force_2T;
>> 				goto found;
>> 			}
>> 			pbsp_highest = pbsp;
>> @@ -75,7 +75,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
>> 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
>> 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
>> -		popts->twoT_en = pbsp_highest->force_2T;
>> +		popts->two_t_en = pbsp_highest->force_2T;
>> 	} else {
>> 		panic("DIMM is not supported by this board");
>> 	}
>> diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c index
>> 5711374..2240972 100644
>> --- a/board/stx/stxgp3/ddr.c
>> +++ b/board/stx/stxgp3/ddr.c
>> @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 	popts->write_data_delay = 3;
>> 
>> 	/* 2T timing enable */
>> -	popts->twoT_en = 1;
>> +	popts->two_t_en = 1;
>> 
>> 	/*
>> 	 * Factors to consider for half-strength driver enable:
>> diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c index
>> 56c87b2..01f92f3 100644
>> --- a/board/stx/stxssa/ddr.c
>> +++ b/board/stx/stxssa/ddr.c
>> @@ -37,7 +37,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 	popts->write_data_delay = 3;
>> 
>> 	/* 2T timing enable */
>> -	popts->twoT_en = 1;
>> +	popts->two_t_en = 1;
>> 
>> 	/*
>> 	 * Factors to consider for half-strength driver enable:
>> diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
>> index 993ae80..b2c461a 100644
>> --- a/board/xes/xpedite550x/ddr.c
>> +++ b/board/xes/xpedite550x/ddr.c
>> @@ -108,7 +108,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
>> 		    ddr_freq <= pbsp->datarate_mhz_high) {
>> 			popts->clk_adjust = pbsp->clk_adjust;
>> 			popts->cpo_override = pbsp->cpo;
>> -			popts->twoT_en = 0;
>> +			popts->two_t_en = 0;
>> 			break;
>> 		}
>> 		pbsp++;
>> diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index
>> 1243a12..9f903ca 100644
>> --- a/doc/README.fsl-ddr
>> +++ b/doc/README.fsl-ddr
>> @@ -391,7 +391,7 @@ Examples of debugging flow
>> 	tRTP_ps = 7500
>> 	tDQSQ_max_ps = 0
>> 	tQHS_ps = 0
>> -	FSL DDR>edit c0 opts ECC_mode 0
>> +	FSL DDR>edit c0 opts ecc_mode 0
>> 	FSL DDR>edit c0 regs cs0_bnds 0x000000FF
>> 	FSL DDR>go
>> 	2 GiB left unmapped
>> --
>> 1.7.9.5
>> 
>> 
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
> 




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